公开(公告)号：US08274148B2

公开(公告)日：2012-09-25

申请号：US12727565

申请日：2010-03-19

申请人： Yasuyuki Yanase ,  Atsunobu Suzuki ,  Yoshio Okayama

发明人： Yasuyuki Yanase ,  Atsunobu Suzuki ,  Yoshio Okayama

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/94 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49537 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

摘要： A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.

摘要翻译： 第一电路元件和第二元件安装成其电极形成表面面向布线层。 与一个面上的布线层一体形成的第一凸块电极基本上贯穿第一绝缘树脂层。 覆盖第一电路元件的元件电极的镀金层和设置在第一凸块电极顶部的镀金层通过Au-Au键合而接合在一起。 与一个面上的布线层一体形成的第二凸块电极基本上贯穿第一绝缘树脂层和第二绝缘树脂层。 覆盖第二电路元件的元件电极的镀金层和设置在第二凸块电极顶部的金镀层通过Au-Au键合而接合在一起。

公开(公告)号：US20100276800A1

公开(公告)日：2010-11-04

申请号：US12727565

申请日：2010-03-19

申请人： Yasuyuki YANASE ,  Atsunobu Suzuki ,  Yoshio Okayama

发明人： Yasuyuki YANASE ,  Atsunobu Suzuki ,  Yoshio Okayama

IPC分类号： H01L23/538

CPC分类号： H01L24/94 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49537 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/02319 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

摘要： A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.

摘要翻译： 第一电路元件和第二元件安装成其电极形成表面面向布线层。 与一个面上的布线层一体形成的第一凸块电极基本上贯穿第一绝缘树脂层。 覆盖第一电路元件的元件电极的镀金层和设置在第一凸块电极顶部的镀金层通过Au-Au键合而接合在一起。 与一个面上的布线层一体形成的第二凸块电极基本上贯穿第一绝缘树脂层和第二绝缘树脂层。 覆盖第二电路元件的元件电极的镀金层和设置在第二凸块电极顶部的金镀层通过Au-Au键合而接合在一起。

公开(公告)号：US20100193946A1

公开(公告)日：2010-08-05

申请号：US12696410

申请日：2010-01-29

申请人： Atsunobu Suzuki ,  Koichi Saito ,  Yasuyuki Yanase ,  Takahiro Fujii

发明人： Atsunobu Suzuki ,  Koichi Saito ,  Yasuyuki Yanase ,  Takahiro Fujii

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.

摘要翻译： 半导体模块包括：绝缘树脂层; 布线层，其设置在绝缘树脂层的一个主表面上，并且包括外部连接区域; 电连接到布线层并且各自形成为从布线层向绝缘树脂层突出的突起电极; 设置在绝缘树脂层的另一个主表面上并且包括连接到凸起电极的器件电极的半导体器件; 以及设置在布线层和绝缘树脂层上以使外部连接区域露出的布线保护层。 在半导体模块中，布线保护层的外边缘部分与半导体器件的外边缘部分接触，从而在侧边缘屏蔽半导体树脂层的至少一部分。

公开(公告)号：US08242598B2

公开(公告)日：2012-08-14

申请号：US12696410

申请日：2010-01-29

申请人： Atsunobu Suzuki ,  Koichi Saito ,  Yasuyuki Yanase ,  Takahiro Fujii

发明人： Atsunobu Suzuki ,  Koichi Saito ,  Yasuyuki Yanase ,  Takahiro Fujii

IPC分类号： H01L23/48

摘要： A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.

公开(公告)号：US08288865B2

公开(公告)日：2012-10-16

申请号：US12696410

申请日：2010-01-29

申请人： Atsunobu Suzuki ,  Koichi Saito ,  Yasuyuki Yanase ,  Takahiro Fujii

发明人： Atsunobu Suzuki ,  Koichi Saito ,  Yasuyuki Yanase ,  Takahiro Fujii

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.

摘要翻译： 半导体模块包括：绝缘树脂层; 布线层，其设置在绝缘树脂层的一个主表面上，并且包括外部连接区域; 电连接到布线层并且各自形成为从布线层向绝缘树脂层突出的突起电极; 设置在绝缘树脂层的另一个主表面上并且包括连接到凸起电极的器件电极的半导体器件; 以及设置在布线层和绝缘树脂层上以使外部连接区域露出的布线保护层。 在半导体模块中，布线保护层的外边缘部分与半导体器件的外边缘部分接触，从而在侧边缘屏蔽半导体树脂层的至少一部分。