-
公开(公告)号：US12094543B2
公开(公告)日：2024-09-17
申请号：US17703998
申请日：2022-03-25
Applicant: Winbond Electronics Corp.
Inventor： Chung-Zen Chen
Abstract: A memory and a sense amplifying device are provided. The sense amplifying device includes a differential amplifier, a first pre-charge circuit, and a control voltage generator. The differential amplifier has a first input terminal and a second input terminal to receive a data signal and a reference signal, respectively. The first pre-charge circuit is coupled to the first input terminal of the differential amplifier. The first pre-charge circuit, based on a power voltage, performs a pre-charge operation on the first input terminal of the differential amplifier according to a pre-charge enable signal and a control voltage. The control voltage generator generates the control voltage according to the power voltage, and the control voltage and the power voltage are in a positive correlation.
-
公开(公告)号：US20240265954A1
公开(公告)日：2024-08-08
申请号：US18410985
申请日：2024-01-11
Applicant: Winbond Electronics Corp.
Inventor： Chung-Zen Chen
CPC classification number: G11C7/1069 , G11C7/08 , G11C7/1063
Abstract: A memory device including a memory cell array, a signal generator, a word line decoder, a bit line decoder, a sensing amplifier circuit and a register circuit is provided. The signal generator generates a control signal according to a wrap around read command. The word line decoder, the bit line decoder, and the sensing amplifier circuit read data stored in the memory cell array according to the wrap around read command, so as to output a first wrap around read data. The register circuit is configured to latch the first wrap around read data and outputs successive wrap around read data according to the control signal and the latched first wrap around read data after the first wrap around read data is output. When the register circuit outputs the successive wrap around read data, the word line decoder, the bit line decoder, and the sensing amplifier circuit are disable.
-
公开(公告)号：US11948648B2
公开(公告)日：2024-04-02
申请号：US17568676
申请日：2022-01-04
Applicant: Winbond Electronics Corp.
Inventor： Chung-Zen Chen
Abstract: A semiconductor memory apparatus including a memory cell array, a switch circuit, and a sensing circuit is provided. The memory cell array includes multiple memory cells. The switch circuit includes at least one switch. Each of the switch receives a control signal and is turned on or off under control of the control signal. When an erase verification is performed, the sensing circuit sequentially receives an erase verification current generated by each of the memory cells through the switch circuit to verify an erase state of the each of the memory cells.
-
公开(公告)号：US20180358063A1
公开(公告)日：2018-12-13
申请号：US15954617
申请日：2018-04-17
Applicant: Winbond Electronics Corp.
Inventor： Chung-Zen Chen
Abstract: A word line decoder circuit located in a memory storage apparatus is provided. The memory storage apparatus includes a memory cell array. The word line decoder circuit includes a word line decoder and a power supply circuit. The word line decoder is coupled to a plurality of word lines of the memory storage apparatus. The power supply circuit is coupled to the word line decoder. The power supply circuit is configured to provide a first power to the word line decoder in a read mode, and provide a second power to the word line decoder in a standby mode. A voltage value of the first power is greater than or less than that of the second power.
-
公开(公告)号：US11983417B2
公开(公告)日：2024-05-14
申请号：US17989661
申请日：2022-11-17
Applicant: Winbond Electronics Corp.
Inventor： Chung-Zen Chen
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0679
Abstract: A power-on read circuit includes a power voltage detector, a first voltage booster, a voltage selector, a reference voltage generator and a read voltage generator. The power voltage detector detects a power voltage to generate a control signal. The first voltage booster generates a first boosted voltage according to the control signal. The voltage selector selects the power voltage or the first boosted voltage to generate a selected voltage. The reference voltage generator receives the selected voltage as an operating power source, and generates a reference voltage based on the selected voltage according to the control signal. The read voltage generator generates a second boosted voltage according to the reference voltage and a clock signal, and generate a read voltage based on the second boosted voltage according to the control signal. The read voltage is provided to a memory cell array to perform a data reading operation.
-
Patent Agency Ranking
公开(公告)号：US20230215504A1
公开(公告)日：2023-07-06
申请号：US17568676
申请日：2022-01-04
Applicant: Winbond Electronics Corp.
Inventor： Chung-Zen Chen
Abstract: A semiconductor memory apparatus including a memory cell array, a switch circuit, and a sensing circuit is provided. The memory cell array includes multiple memory cells. The switch circuit includes at least one switch. Each of the switch receives a control signal and is turned on or off under control of the control signal. When an erase verification is performed, the sensing circuit sequentially receives an erase verification current generated by each of the memory cells through the switch circuit to verify an erase state of the each of the memory cells.
-
公开(公告)号：US20230214131A1
公开(公告)日：2023-07-06
申请号：US17989661
申请日：2022-11-17
Applicant: Winbond Electronics Corp.
Inventor： Chung-Zen Chen
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0679
Abstract: A power-on read circuit includes a power voltage detector, a first voltage booster, a voltage selector, a reference voltage generator and a read voltage generator. The power voltage detector detects a power voltage to generate a control signal. The first voltage booster generates a first boosted voltage according to the control signal. The voltage selector selects the power voltage or the first boosted voltage to generate a selected voltage. The reference voltage generator receives the selected voltage as an operating power source, and generates a reference voltage based on the selected voltage according to the control signal. The read voltage generator generates a second boosted voltage according to the reference voltage and a clock signal, and generate a read voltage based on the second boosted voltage according to the control signal. The read voltage is provided to a memory cell array to perform a data reading operation.
-
公开(公告)号：US10510389B2
公开(公告)日：2019-12-17
申请号：US15954617
申请日：2018-04-17
Applicant: Winbond Electronics Corp.
Inventor： Chung-Zen Chen
Abstract: A word line decoder circuit located in a memory storage apparatus is provided. The memory storage apparatus includes a memory cell array. The word line decoder circuit includes a word line decoder and a power supply circuit. The word line decoder is coupled to a plurality of word lines of the memory storage apparatus. The power supply circuit is coupled to the word line decoder. The power supply circuit is configured to provide a first power to the word line decoder in a read mode, and provide a second power to the word line decoder in a standby mode. A voltage value of the first power is greater than or less than that of the second power.
-
公开(公告)号：US20180335970A1
公开(公告)日：2018-11-22
申请号：US15871124
申请日：2018-01-15
Applicant: Winbond Electronics Corp.
Inventor： Chung-Zen Chen
CPC classification number: G06F3/0634 , G06F3/0604 , G06F3/0625 , G06F3/0659 , G06F3/0679 , G11C5/145 , G11C5/148 , G11C16/08 , G11C16/30
Abstract: A flash memory storage apparatus having a plurality of operation modes is provided. The flash memory storage apparatus includes a memory controller circuit and a memory cell array. The memory controller circuit is configured to control the flash memory storage apparatus to operate in one of the operation modes. The operation modes include a low standby current mode. The memory cell array is coupled to the memory controller circuit. The memory cell array is configured to store data. The data includes read-only memory data. The memory controller circuit controls the flash memory storage apparatus to enter the low standby current mode according to a first command. The memory controller circuit wakes up the flash memory storage apparatus from the low standby current mode according to a second command. When the flash memory storage apparatus operates in the low standby current mode, the read-only memory data is kept.
-
公开(公告)号：US20230307064A1
公开(公告)日：2023-09-28
申请号：US17703998
申请日：2022-03-25
Applicant: Winbond Electronics Corp.
Inventor： Chung-Zen Chen
Abstract: A memory and a sense amplifying device are provided. The sense amplifying device includes a differential amplifier, a first pre-charge circuit, and a control voltage generator. The differential amplifier has a first input terminal and a second input terminal to receive a data signal and a reference signal, respectively. The first pre-charge circuit is coupled to the first input terminal of the differential amplifier. The first pre-charge circuit, based on a power voltage, performs a pre-charge operation on the first input terminal of the differential amplifier according to a pre-charge enable signal and a control voltage. The control voltage generator generates the control voltage according to the power voltage, and the control voltage and the power voltage are in a positive correlation.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.013 seconds)
