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    Field programmable gate array utilizing dedicated memory stacks in a vertical layer format
    1.
    发明申请
    Field programmable gate array utilizing dedicated memory stacks in a vertical layer format 有权
    利用垂直层格式的专用存储器堆栈的现场可编程门阵列

    公开(公告)号：US20080074144A1

    公开(公告)日：2008-03-27

    申请号：US11897938

    申请日：2007-08-31

    Applicant: Volkan Ozguz ,  Randolph Carlson ,  Keith Gann ,  John Leon ,  W. Boyd

    Inventor： Volkan Ozguz ,  Randolph Carlson ,  Keith Gann ,  John Leon ,  W. Boyd

    IPC: H03K19/173

    CPC classification number: H03K19/1776 ,  G01R31/318519 ,  G06F9/3802 ,  H03K19/177 ,  H03K19/17792

    Abstract: A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.

    Abstract translation: 现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。 绝对最大字宽度可以与m.times.N一样大m其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。

    Anti-tamper module
    3.
    发明申请
    Anti-tamper module 有权
    防篡改模块

    公开(公告)号：US20060087883A1

    公开(公告)日：2006-04-27

    申请号：US11248659

    申请日：2005-10-11

    Applicant: Volkan Ozguz ,  John Leon

    Inventor： Volkan Ozguz ,  John Leon

    IPC: G11C16/04 ,  H01L23/02 ,  H01L21/50 ,  H01L21/82 ,  G08B13/14 ,  G08B21/00

    CPC classification number: H01L23/576 ,  G06F21/87 ,  H01L23/48 ,  H01L23/49816 ,  H01L25/0657 ,  H01L27/02 ,  H01L2223/6677 ,  H01L2224/16 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/0401

    Abstract: An anti-tamper module is provided for protecting the contents and functionality of an integrated circuit incorporated in the module. The anti-tamper module is arranged in a stacked configuration having multiple layers. A connection layer is provided for connecting the module to an external system. A configurable logic device is provided for routing connections between the integrated circuit and the connection layer. Specifically, the configurable logic device is programmable to create logical circuits connecting at least one of the input/output connectors of the integrated circuit to at least one of the input/output connectors of the connection layer. Configuration information for programming the reconfigurable logic device is stored in a memory within the module.

    Abstract translation: 提供防篡改模块，用于保护组合在模块中的集成电路的内容和功能。 防篡改模块被布置成具有多层的堆叠构造。 提供连接层将模块连接到外部系统。 提供了一种用于在集成电路和连接层之间路由连接的可配置逻辑器件。 具体地，可配置逻辑器件是可编程的，以创建将集成电路的至少一个输入/输出连接器连接到连接层的至少一个输入/输出连接器的逻辑电路。 用于编程可重构逻辑器件的配置信息存储在模块内的存储器中。

    Secure Anti-Tamper Integrated Layer Security Device Comprising Nano-Structures
    4.
    发明申请
    Secure Anti-Tamper Integrated Layer Security Device Comprising Nano-Structures 审中-公开
    包含纳米结构的安全防篡改集成层安全设备

    公开(公告)号：US20110227603A1

    公开(公告)日：2011-09-22

    申请号：US13045880

    申请日：2011-03-11

    Applicant: John Leon ,  James Yamaguchi ,  W. Eric Boyd ,  Volkan Ozguz

    Inventor： John Leon ,  James Yamaguchi ,  W. Eric Boyd ,  Volkan Ozguz

    IPC: H03K19/00 ,  H02H3/08 ,  G01R27/26 ,  G01R27/08

    CPC classification number: H01L23/576 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/16 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A device and method using one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. The nano-structure is in connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the nano-structure is breached or altered. One or more electrically conductive nano-structures interconnect and reroute one or more electrical connections between one or more ICs to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device. microscope.

    Abstract translation: 限定在微电子电路的一个或多个表面上的一个或多个导电纳米结构的装置和方法，所述微电子电路例如集成电路管芯，微电子电路封装堆叠的微电子电路封装，或者在一个或多个层的表面上 一堆包含一个或多个IC的层。 纳米结构与监控电路相连，并用作“跳闸线”，以检测未经授权篡改设备或模块。 这种监视电路可以包括芯片或封装内的诸如电路内或模块内电池的电源和“归零”电路，以在纳米结构被破坏或改变时擦除存储器的内容物。 一个或多个导电纳米结构互连并重新路由一个或多个IC之间的一个或多个电连接，以在芯片或堆栈上产生“不可见”的电连接集合，以模糊设备的反向工程尝试。 显微镜。

    Tamper-resistant electronic circuit and module incorporating electrically conductive nano-structures
    5.
    发明申请
    Tamper-resistant electronic circuit and module incorporating electrically conductive nano-structures 审中-公开
    具有防篡改电子电路和包含导电纳米结构的模块

    公开(公告)号：US20110031982A1

    公开(公告)日：2011-02-10

    申请号：US12806127

    申请日：2010-08-04

    Applicant: John Leon ,  James Yamaguchi ,  Volkan Ozguz ,  W. Eric Boyd

    Inventor： John Leon ,  James Yamaguchi ,  Volkan Ozguz ,  W. Eric Boyd

    IPC: G01R27/28 ,  H02H3/08 ,  H05K7/00

    CPC classification number: H01L23/576 ,  H01L25/0657 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: A device and method are disclosed comprising one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package (such as a TSOP, BGA or other prepackaged IC) a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs.In one embodiment, the electrically conductive nano-structure is in electrical connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the electrically conductive nano-structure is breached or altered. The device may be configured to blow one or more fuses or overcurrent protection devices when the electrically conductive nano-structure is breached or altered.In a further embodiment, one or more electrically conductive nano-structures are used to interconnect and reroute one or more electrical connections between one or more ICs (or dummy leads and vias) to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device, i.e., a set of connections that cannot be observed by standard test means such as by X-ray or conventional microscope.

    Abstract translation: 公开了一种器件和方法，其包括限定在微电子电路的一个或多个表面上的一个或多个导电纳米结构，例如集成电路管芯，微电子电路封装（例如TSOP，BGA或其它预封装IC）堆叠微电子 或者在包含一个或多个IC的层叠层中的一个或多个层的表面上。 在一个实施例中，导电纳米结构与监控电路电连接，并用作“跳闸线”，以检测未经授权的篡改设备或模块。 这样的监视电路可以包括诸如电路内或模块内电池的电源和芯片或封装内的“零化”电路，以在导电纳米结构被破坏或改变时擦除存储器的内容物。 该装置可以被配置为当导电纳米结构被破坏或改变时吹送一个或多个保险丝或过电流保护装置。 在另一个实施例中，使用一个或多个导电纳米结构来互连和重新路由一个或多个IC（或虚拟引线和通孔）之间的一个或多个电连接，以在芯片上产生“不可见”的电连接集合，或 堆叠以模糊化设备的反向工程，即通过X射线或常规显微镜的标准测试手段无法观察到的一组连接。

    Apparatus comprising artificial neuronal assembly
    9.
    发明授权
    Apparatus comprising artificial neuronal assembly 有权
    装置包括人造神经元组装

    公开(公告)号：US08510244B2

    公开(公告)日：2013-08-13

    申请号：US12661537

    申请日：2010-03-18

    Applicant: John C. Carson ,  Volkan Ozguz

    Inventor： John C. Carson ,  Volkan Ozguz

    IPC: G06E1/00 ,  G06E3/00 ,  G06F15/18 ,  G06G7/00

    CPC classification number: G06N3/02

    Abstract: An artificial synapse array and virtual neural space are disclosed.More specifically, a cognitive sensor system and method are disclosed comprising a massively parallel convolution processor capable of, for instance, situationally dependent identification of salient features in a scene of interest by emulating the cortical hierarchy found in the human retina and visual cortex.

    Abstract translation: 公开了人造突触阵列和虚拟神经空间。 更具体地，公开了一种认知传感器系统和方法，其包括大规模平行卷积处理器，其能够例如通过模拟在人类视网膜和视觉皮层中发现的皮质层级来情境依赖地识别感兴趣的场景中的显着特征。

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