公开(公告)号：US12232425B2

公开(公告)日：2025-02-18

申请号：US18515273

申请日：2023-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Dong-Ming Wu ,  Chen-Yi Weng ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang

IPC: G11C11/00 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

公开(公告)号：US12201032B2

公开(公告)日：2025-01-14

申请号：US17223025

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H10N50/85 ,  H10B61/00 ,  H10N50/80 ,  H10N50/01

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

公开(公告)号：US20240431214A1

公开(公告)日：2024-12-26

申请号：US18224050

申请日：2023-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang

IPC: H10N50/01 ,  H01F10/32 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an inter-metal dielectric (IMD) layer on a substrate, forming a contact hole in the IMD layer, forming a barrier layer and a metal layer in the contact hole, planarizing the metal layer, forming a spin orbit torque (SOT) layer on the barrier layer and the metal layer, and then forming a magnetic tunneling junction (MTJ) on the SOT layer.

公开(公告)号：US20240415024A1

公开(公告)日：2024-12-12

申请号：US18216610

申请日：2023-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang

IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A magnetoresistive random access memory device includes a bottom electrode, a spin orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) and a top electrode. The bottom electrode includes a first layer and a second layer connected with the first layer. A material of the first layer includes Tax1Ny1, a material of the second layer includes Tax2Ny2, and the following relationships are satisfied: y2/x2>1, y1/x1≥1, and y2/x2>y1/x1. The SOT layer is disposed on the bottom electrode. The MTJ is disposed on the SOT layer. The top electrode is disposed on the MTJ.

公开(公告)号：US20240365563A1

公开(公告)日：2024-10-31

申请号：US18762663

申请日：2024-07-03

Applicant: UNITED MICROELECTRONICS CORP

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen ,  Wei Chen

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device including a magnetic tunneling junction (MTJ) and a hard mask on a substrate, a first inter-metal dielectric (IMD) layer around the MTJ, a first metal interconnection adjacent to the MTJ, a first barrier layer and a channel layer on the first IMD layer to directly contact the hard mask and electrically connect the MTJ and the first metal interconnection, and a stop layer around the channel layer.

公开(公告)号：US12108680B2

公开(公告)日：2024-10-01

申请号：US18135758

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H10N50/01 ,  H10N50/80 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/01 ,  H10N50/80 ,  H10B61/00 ,  H10N50/85

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.

公开(公告)号：US11957061B2

公开(公告)日：2024-04-09

申请号：US18200592

申请日：2023-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Ching-Hua Hsu ,  Hung-Yueh Chen

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  H10B61/22 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

公开(公告)号：US11917923B2

公开(公告)日：2024-02-27

申请号：US17242322

申请日：2021-04-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ching-Hua Hsu ,  Si-Han Tsai ,  Shun-Yu Huang ,  Chen-Yi Weng ,  Ju-Chun Fan ,  Che-Wei Chang ,  Yi-Yu Lin ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Ya-Jyuan Hung

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H01L27/22 ,  H01L43/12

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

公开(公告)号：US20240065108A1

公开(公告)日：2024-02-22

申请号：US17944242

申请日：2022-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Po-Kai Hsu

IPC: H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/10

CPC classification number: H01L43/12 ,  H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L27/222 ,  H01L43/10

Abstract: The high-density MRAM device of the present invention has a second interlayer dielectric (ILD) layer covering the capping layer in the MRAM cell array area and the logic area. The thickness of the second ILD layer in the MRAM cell array area is greater than that in the logic area. The composition of the second ILD layer in the logic area is different from the composition of the second ILD layer in the MRAM cell array area.

公开(公告)号：US20240057483A1

公开(公告)日：2024-02-15

申请号：US17903998

申请日：2022-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L43/12

Abstract: A magnetic memory device includes a bottom electrode layer, a magnetic tunneling junction (MTJ) stack disposed on the bottom electrode layer, a capping layer disposed on the MTJ stack, and a top electrode layer disposed on the capping layer. The top electrode layer comprises RuO2.