公开(公告)号：US10276367B1

公开(公告)日：2019-04-30

申请号：US15865263

申请日：2018-01-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Jen-Chieh Lin ,  Wen-Chin Lin ,  Yu-Ting Li

IPC: H01L21/02 ,  H01L21/302 ,  H01L21/321 ,  H01L21/768 ,  H01L21/306

Abstract: A method for improving wafer surface uniformity is disclosed. A wafer including a first region and a second region is provided. The first region and the second region have different pattern densities. A conductive layer is formed on the wafer. A buffer layer is then formed on the conductive layer. The buffer layer is polished until the conductive layer is exposed. A portion of the conductive layer and the remaining buffer layer are etched away.

公开(公告)号：US20160351674A1

公开(公告)日：2016-12-01

申请号：US15232796

申请日：2016-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Chih-Hsun Lin ,  Tzu-Hsiang Hung ,  Wu-Sian Sie ,  I-Lun Hung ,  Wen-Chin Lin ,  Chun-Tsen Lu

IPC: H01L29/423 ,  H01L21/66 ,  H01L29/51 ,  H01L21/324 ,  H01L29/66 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L29/42364 ,  H01L21/02271 ,  H01L21/02354 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/823437 ,  H01L22/12 ,  H01L22/20 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface. A semiconductor structure formed by said semiconductor process is also provided.

Abstract translation: 半导体工艺包括以下步骤。 电介质层形成在基板上，其中电介质层至少具有来自第一顶表面的凹陷。 形成可收缩层以覆盖电介质层，其中可收缩层具有第二顶表面。 执行处理过程以根据第二顶表面的形貌收缩可收缩层的一部分，从而使第二顶表面变平。 还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US20150004780A1

公开(公告)日：2015-01-01

申请号：US14490679

申请日：2014-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsun-Min Cheng ,  Min-Chuan Tsai ,  Chih-Chien Liu ,  Jen-Chieh Lin ,  Pei-Ying Li ,  Shao-Wei Wang ,  Mon-Sen Lin ,  Ching-Ling Lin

IPC: H01L29/49 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/435 ,  H01L29/51 ,  H01L29/66045 ,  H01L29/66545 ,  H01L29/78

Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Abstract translation: 位于基板上的金属栅极结构包括栅介质层，金属层和氮化铝钛金属层。 栅介质层位于衬底上。 金属层位于栅极电介质层上。 氮化铝钛金属层位于金属层上。

公开(公告)号：US10943910B2

公开(公告)日：2021-03-09

申请号：US16151337

申请日：2018-10-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/10 ,  H01L27/108 ,  H01L27/06 ,  H01L21/8234

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US20160336269A1

公开(公告)日：2016-11-17

申请号：US14709500

申请日：2015-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Shu Min Huang ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Pei-Yu Lee ,  Min-Chuan Tsai ,  Chih-Hsun Lin ,  Wu-Sian Sie ,  Jen-Chieh Lin

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/7684 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76874 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor process includes the following steps. A dielectric layer having a recess is formed on a substrate. A barrier layer is formed to cover the recess, thereby the barrier layer having two sidewall parts. A conductive layer is formed on the barrier layer by an atomic layer deposition process, thereby the conductive layer having two sidewall parts. The two sidewall parts of the conductive layer are pulled down. A conductive material fills the recess and has a part contacting the two sidewall parts of the barrier layer protruding from the two sidewall parts of the conductive layer, wherein the equilibrium potential difference between the barrier layer and the conductive layer is different from the equilibrium potential difference between the barrier layer and the conductive material. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成具有凹部的电介质层。 形成阻挡层以覆盖凹部，由此阻挡层具有两个侧壁部分。 通过原子层沉积工艺在阻挡层上形成导电层，由此导电层具有两个侧壁部分。 导电层的两个侧壁部分被拉下。 导电材料填充凹部，并且具有接触从导电层的两个侧壁部分突出的阻挡层的两个侧壁部分的部分，其中阻挡层和导电层之间的平衡电位差不同于平衡电位差 在阻挡层和导电材料之间。 此外，本发明还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US09281374B2

公开(公告)日：2016-03-08

申请号：US14490679

申请日：2014-09-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsun-Min Cheng ,  Min-Chuan Tsai ,  Chih-Chien Liu ,  Jen-Chieh Lin ,  Pei-Ying Li ,  Shao-Wei Wang ,  Mon-Sen Lin ,  Ching-Ling Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/43 ,  H01L29/772 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/435 ,  H01L29/51 ,  H01L29/66045 ,  H01L29/66545 ,  H01L29/78

Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Abstract translation: 位于基板上的金属栅极结构包括栅介质层，金属层和氮化铝钛金属层。 栅介质层位于衬底上。 金属层位于栅极电介质层上。 氮化铝钛金属层位于金属层上。

公开(公告)号：US10923481B2

公开(公告)日：2021-02-16

申请号：US16151323

申请日：2018-10-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/10 ,  H01L27/108 ,  H01L27/06 ,  H01L21/8234

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

公开(公告)号：US10262869B2

公开(公告)日：2019-04-16

申请号：US15904405

申请日：2018-02-25

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Jen-Chieh Lin ,  Lee-Yuan Chen ,  Wen-Chin Lin ,  Chi-Lune Huang ,  Pi-Hung Chuang ,  Tai-Lin Chen ,  Sun-Hong Chen

IPC: H01L21/3105 ,  H01L21/308 ,  H01L21/768 ,  H01L21/321

Abstract: A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.

公开(公告)号：US20160013100A1

公开(公告)日：2016-01-14

申请号：US14461433

申请日：2014-08-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Po-Cheng Huang ,  Chih-Chien Liu ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Chang-Hung Kung ,  Wen-Chin Lin ,  Chih-Hsun Lin ,  Kuo-Chin Hung

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/32136 ,  H01L21/3215 ,  H01L21/76859 ,  H01L21/76865 ,  H01L21/76874 ,  H01L21/76879 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

Abstract: A via structure and a method of forming the same are provided. In the forming method of the present invention, a via is formed in a dielectric layer. Next, a U-shaped seed layer is formed in the via. After that, a conductive material is selectively formed in the via to form a conductive bulk layer in the via. Through the present invention, the purposes of effectively removing the overhang adjacent to the opening of the via and protecting the U-shaped seed layer in the via can be achieved.

Abstract translation: 提供通孔结构及其形成方法。 在本发明的形成方法中，在电介质层中形成通孔。 接下来，在通孔中形成U形种子层。 之后，在通路中选择性地形成导电材料，以在通孔中形成导电体层。 通过本发明，可以实现有效地去除邻近通孔开口的突出端并保护通孔中的U形种子层的目的。

公开(公告)号：US20190043866A1

公开(公告)日：2019-02-07

申请号：US16151337

申请日：2018-10-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/108

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.