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公开(公告)号：US20240364569A1
公开(公告)日：2024-10-31
申请号：US18632062
申请日：2024-04-10
Applicant: Texas Instruments Incorporated
Inventor： Raju Kharataram Chaudhari , Aswath VS , Sriram Murali , Jaiganesh Balakrishnan , Sreenath Narayanan Potty , Kapil Kumar
CPC classification number: H04L27/2618 , H04B1/0475
Abstract: An example apparatus includes: crest factor reduction circuitry having a signal input and a peak cancellation waveform input; and peak cancellation waveform generator circuitry including: carrier profile analyzer circuitry having a signal input coupled to the signal input of the crest factor reduction circuitry, and having a carrier profile output; waveform construction circuitry having a carrier profile input coupled to the carrier profile output of the carrier profile analyzer circuitry, having a second input, and having a peak cancellation waveform output coupled to the peak cancellation waveform input of the crest factor reduction circuitry; and profile change detector circuitry having a carrier profile input coupled to the carrier profile output of the carrier profile analyzer circuitry, and having an output coupled to the second input of the waveform construction circuitry.
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公开(公告)号：US09178525B2
公开(公告)日：2015-11-03
申请号：US14656122
申请日：2015-03-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sthanunathan Ramakrishnan , Sreenath Narayanan Potty
CPC classification number: H03M1/121 , H03M1/06 , H03M1/0626 , H03M1/0639 , H03M1/1205 , H03M1/1215
Abstract: A mismatch corrector can include a correction path comprising a plurality of parallel branches that each includes a correction filter that applies a respective one of a plurality of time domain filter coefficients that corresponds to a function of a mismatch profile of an interleaved analog-to-digital (IADC) signal on the IADC signal. The mismatch corrector can also include a delay path that delays the IADC signal by a predetermined number of samples to provide a delayed version of the IADC signal. The mismatch corrector can further include a summer to subtract an output of each correction filter from the delayed version of the IADC signal to generate a corrected IADC signal.
Abstract translation: 不匹配校正器可以包括校正路径，其包括多个并行分支，每个分支包括校正滤波器，校正滤波器应用与交织的模数转换器的失配曲线的函数相对应的多个时域滤波器系数中的相应一个 （IADC）信号。 不匹配校正器还可以包括将IADC信号延迟预定数量的采样以提供IADC信号的延迟版本的延迟路径。 不匹配校正器还可以包括加法器，以从IADC信号的延迟版本中减去每个校正滤波器的输出，以产生校正的IADC信号。
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公开(公告)号：US20150185283A1
公开(公告)日：2015-07-02
申请号：US14145293
申请日：2013-12-31
Applicant: Texas Instruments Incorporated
IPC: G01R31/3177 , G01R31/317
CPC classification number: G01R31/318335 , G01R31/31725 , G01R31/31727 , G01R31/3177 , G01R31/318547 , G01R31/318552
Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes a scan compression architecture driven by a scan clock and generates M scan outputs, where M is an integer. A clock divider is configured to divide the scan clock by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic is coupled to the scan compression architecture and generates kM slow scan outputs in response to the M scan outputs and the k number of phase shifted scan clocks. The packing logic further includes M number of packing elements and each packing element of the M number of packing elements receives a scan output of the M scan outputs. Each packing element includes k number of flip-flops and each flip-flop of the k number of flip-flops in a packing element receives a scan output of the M scan outputs. Each flip-flop receives a phase-shifted scan clock of the k number of phase-shifted scan clocks, such that each flip-flop generates a slow scan output of the kM slow scan outputs in response to the scan output and the phase-shifted scan clock.
Abstract translation: 实施例提供了一种用于测试集成电路的电路。 该电路包括由扫描时钟驱动的扫描压缩架构并产生M个扫描输出，其中M是整数。 时钟分频器被配置为将扫描时钟除以k以产生k个相移扫描时钟，其中k是整数。 打包逻辑耦合到扫描压缩架构，并响应于M扫描输出和k个相移扫描时钟产生kM慢速扫描输出。 包装逻辑还包括M个包装元件，并且M个包装元件的每个包装元件接收M个扫描输出的扫描输出。 每个封装元件包括k个触发器，并且打包元件中k个触发器的每个触发器接收M个扫描输出的扫描输出。 每个触发器接收k个相移扫描时钟的相移扫描时钟，使得每个触发器响应于扫描输出和相移而产生kM慢扫描输出的慢扫描输出 扫描时钟。
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4.发明授权Interference mitigation output frequency determined by division factors selected randomly 有权干扰减轻输出频率由随机选择的分频因子决定公开(公告)号：US08981821B2
公开(公告)日：2015-03-17
申请号：US13739256
申请日：2013-01-11
Applicant: Texas Instruments Incorporated
Inventor： Sreenath Narayanan Potty , Jasbir Singh Nayyar , Vivek Singhal
Abstract: Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit.
Abstract translation: 公开了几种方法和电路，其被配置为减轻可操作在IC中的至少一个受害电路的干扰频率范围内的第一时钟信号上的至少一个侵扰电路的信号干扰。 在一个实施例中，信号干扰减轻电路被配置为与侵扰电路相关联并且包括时钟分频器电路和控制电路。 时钟分频器电路被配置为基于第二时钟信号和分频因子模式产生第一时钟信号。 控制电路与时钟分频器电路耦合，并配置为确定分频系数模式，并将分频系数模式提供给时钟分频器电路。 分割因子模式包括基于多个随机数随机选择的多个分频因子，并且被配置为控制与信号干扰减轻电路相关联的吞吐量频率。
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公开(公告)号：US20140197875A1
公开(公告)日：2014-07-17
申请号：US13739256
申请日：2013-01-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sreenath Narayanan Potty , Jasbir Singh Nayyar , Vivek Singhal
IPC: G06G7/16
Abstract: Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit.
Abstract translation: 公开了几种方法和电路，其被配置为减轻可操作在IC中的至少一个受害电路的干扰频率范围内的第一时钟信号上的至少一个侵扰电路的信号干扰。 在一个实施例中，信号干扰减轻电路被配置为与侵扰电路相关联并且包括时钟分频器电路和控制电路。 时钟分频器电路被配置为基于第二时钟信号和分频因子模式产生第一时钟信号。 控制电路与时钟分频器电路耦合，并配置为确定分频系数模式，并将分频系数模式提供给时钟分频器电路。 分割因子模式包括基于多个随机数随机选择的多个分频因子，并且被配置为控制与信号干扰减轻电路相关联的吞吐量频率。
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Patent Agency Ranking
公开(公告)号：US10541703B2
公开(公告)日：2020-01-21
申请号：US16029539
申请日：2018-07-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sthanunathan Ramakrishnan , Sashidharan Venkatraman , Jaiganesh Balakrishnan , Sreenath Narayanan Potty
Abstract: An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA subranges). The ADC includes an IL mismatch estimation engine in the digital signal path, with an estimation subrange blanker, and an IL mismatch estimator. The estimation subrange blanker is coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting that is within an allocated DSA subrange (DSA active data within an DSA allocated subrange). The IL mismatch estimator aggregates, during each aggregation cycle, IL mismatch estimation data based on the selected DSA active data within the DSA allocated subrange, generates an estimate of IL mismatch (IL mismatch estimate) based on the aggregated IL mismatch estimation data, generates IL mismatch correction parameters based on the aggregated IL mismatch estimation data, and generates IL mismatch estimate uncertainty data corresponding to an uncertainty in the IL mismatch estimate used to generate the associated IL mismatch correction parameters for the DSA allocated subrange. A DSA statistics collector to collect a distribution of DSA settings over a pre-defined time period (DSA setting distribution statistics). An estimation subrange allocator coupled to receive DSA setting distribution statistics, and the IL mismatch estimate uncertainty data, and to provide to the estimation subrange blanker the DSA subrange allocation signal according to a pre-defined allocation strategy.
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公开(公告)号：US09970987B2
公开(公告)日：2018-05-15
申请号：US15239279
申请日：2016-08-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sreenath Narayanan Potty , Rajesh Mittal , Mudasir Shafat Kawoosa , Vivek Singhal
IPC: G01R31/3183 , G01R31/3185 , G01R31/317 , G01R31/3177
CPC classification number: G01R31/3177 , G01R31/3172 , G01R31/31723 , G01R31/31727 , G01R31/3183 , G01R31/318335 , G01R31/318533 , G01R31/318544 , G01R31/318563
Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.
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公开(公告)号：US09923737B2
公开(公告)日：2018-03-20
申请号：US15246248
申请日：2016-08-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jaiganesh Balakrishnan , Jawaharlal Tangudu , Sreenath Narayanan Potty
IPC: H04L27/14 , H03K9/00 , H04L25/03 , H04L12/741 , H04L12/26
CPC classification number: H04L25/03006 , H04L43/022 , H04L45/745
Abstract: A re-sampler comprises: a plurality of multipliers configured to receive an input sample; and a plurality of accumulators coupled to the multipliers and configured to form multiplier-accumulator (MAC) units with the multipliers, wherein the MAC units are configured to: compute partial products from the input sample, accumulate the partial products over clock cycles, and sequentially generate output samples based on the computing and the accumulating. A method comprises: receiving input samples; computing partial products from the input samples; accumulating the partial products over clock cycles; and sequentially generating output samples based on the computing and the accumulating.
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公开(公告)号：US20170115400A1
公开(公告)日：2017-04-27
申请号：US14919710
申请日：2015-10-21
Applicant: Texas Instruments Incorporated
Inventor： Jasbir Singh Nayyar , Sreenath Narayanan Potty , Sunil Chomal
IPC: G01S19/30
CPC classification number: G01S19/30 , H04B1/70752
Abstract: A personal navigation device includes a correlator for processing GNNS signals from a constellation of satellites A signal is received from a navigation beacon containing a repeating code word, in which the code word includes a number N of samples corresponding to N phases, and in which reception of each code word occurs within a defined time period T. The sequence of N code samples is correlated with a known code word to determine a maximum value of correlation for a particular phase of the received signal. The correlation is performed using a correlator of size M, in which M is less than N, such that N/M=P complete correlations for a partial code phase are performed such that each correlation of a partial code phase is performed within a time period of approximately T/P. All P correlations of partial code phases are completed within time T.
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10.发明授权公开(公告)号：US09448284B2
公开(公告)日：2016-09-20
申请号：US14272760
申请日：2014-05-08
Applicant: Texas Instruments Incorporated
Inventor： Sreenath Narayanan Potty , Rajesh Mittal , Mudasir Shafat Kawoosa , Vivek Singhal
IPC: G01R31/3183 , G01R31/3185 , G01R31/317 , G01R31/3177
CPC classification number: G01R31/3177 , G01R31/3172 , G01R31/31723 , G01R31/31727 , G01R31/3183 , G01R31/318335 , G01R31/318533 , G01R31/318544 , G01R31/318563
Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.
Abstract translation: 实施例提供了一种用于测试集成电路的电路。 该电路包括输入转换器，其接收N个扫描输入并产生M个伪扫描输入，其中M和N是整数。 扫描压缩架构耦合到输入转换器并响应于M个伪扫描输入产生P个伪扫描输出。 输出转换器耦合到扫描压缩架构并响应于P伪扫描输出产生Q扫描输出，其中P和Q是整数。 输入转换器以第一频率接收N个扫描输入并以第二频率产生M个伪扫描输入，并且输出转换器以第二频率接收P个伪扫描输出，并以第一个频率产生Q个扫描输出。
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