公开(公告)号：US11899063B2

公开(公告)日：2024-02-13

申请号：US17809616

申请日：2022-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mudasir Shafat Kawoosa ,  Rajesh Mittal

IPC: G01R31/3177 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318385 ,  G01R31/318547

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

公开(公告)号：US11408936B2

公开(公告)日：2022-08-09

申请号：US16920806

申请日：2020-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mudasir Shafat Kawoosa ,  Rajesh Mittal

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3185

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

公开(公告)号：US20200333397A1

公开(公告)日：2020-10-22

申请号：US16920806

申请日：2020-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mudasir Shafat Kawoosa ,  Rajesh Mittal

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3185

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

公开(公告)号：US20160356849A1

公开(公告)日：2016-12-08

申请号：US15239279

申请日：2016-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenath Narayanan Potty ,  Rajesh Mittal ,  Mudasir Shafat Kawoosa ,  Vivek Singhal

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3183 ,  G01R31/318335 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318563

Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

Abstract translation: 实施例提供了一种用于测试集成电路的电路。 该电路包括输入转换器，其接收N个扫描输入并产生M个伪扫描输入，其中M和N是整数。 扫描压缩架构耦合到输入转换器并响应于M个伪扫描输入产生P个伪扫描输出。 输出转换器耦合到扫描压缩架构并响应于P伪扫描输出产生Q扫描输出，其中P和Q是整数。 输入转换器以第一频率接收N个扫描输入并以第二频率产生M个伪扫描输入，并且输出转换器以第二频率接收P个伪扫描输出，并以第一个频率产生Q个扫描输出。

公开(公告)号：US20220326303A1

公开(公告)日：2022-10-13

申请号：US17809616

申请日：2022-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mudasir Shafat Kawoosa ,  Rajesh Mittal

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3185

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

公开(公告)号：US10739402B2

公开(公告)日：2020-08-11

申请号：US16039067

申请日：2018-07-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mudasir Shafat Kawoosa ,  Rajesh Mittal

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3185

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.

公开(公告)号：US09970987B2

公开(公告)日：2018-05-15

申请号：US15239279

申请日：2016-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenath Narayanan Potty ,  Rajesh Mittal ,  Mudasir Shafat Kawoosa ,  Vivek Singhal

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3183 ,  G01R31/318335 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318563

Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

公开(公告)号：US09772376B1

公开(公告)日：2017-09-26

申请号：US15143439

申请日：2016-04-29

Applicant: Texas Instruments Incorporated

Inventor： Mudasir Shafat Kawoosa ,  Rajesh Mittal

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319

CPC classification number: G01R31/3177 ,  G01R31/31701 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/318572 ,  G01R31/31926

Abstract: An integrated circuit with functional circuitry and testing circuitry, the testing circuitry having a state machine operable in a plurality of different states. The integrated circuit also has a pin for receiving a signal, wherein the state machine is operable to transition between states in response to a change in level of the signal. Circuitry couples the signal of the pin, in a first level, to the state machine in a first time period for causing the state machine to enter a predetermined state, and circuitry maintains the signal in the first level to the state machine in a second time period for maintaining the state machine in the predetermined state. Also during the second time period, circuitry couples data received at the pin to a destination circuit other than the state machine, wherein the destination circuit is operable to perform plural successive scan tests using data from the pin without a power on reset of the functional circuitry.

公开(公告)号：US09448284B2

公开(公告)日：2016-09-20

申请号：US14272760

申请日：2014-05-08

Applicant: Texas Instruments Incorporated

Inventor： Sreenath Narayanan Potty ,  Rajesh Mittal ,  Mudasir Shafat Kawoosa ,  Vivek Singhal

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3183 ,  G01R31/318335 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318563

Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

Abstract translation: 实施例提供了一种用于测试集成电路的电路。 该电路包括输入转换器，其接收N个扫描输入并产生M个伪扫描输入，其中M和N是整数。 扫描压缩架构耦合到输入转换器并响应于M个伪扫描输入产生P个伪扫描输出。 输出转换器耦合到扫描压缩架构并响应于P伪扫描输出产生Q扫描输出，其中P和Q是整数。 输入转换器以第一频率接收N个扫描输入并以第二频率产生M个伪扫描输入，并且输出转换器以第二频率接收P个伪扫描输出，并以第一个频率产生Q个扫描输出。

公开(公告)号：US20180045778A1

公开(公告)日：2018-02-15

申请号：US15722975

申请日：2017-10-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rajesh Mittal ,  Rajat Mehrotra

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3177

CPC classification number: G01R31/31713 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318572

Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.