公开(公告)号：US20060170041A1

公开(公告)日：2006-08-03

申请号：US11335602

申请日：2006-01-20

Applicant: Takeshi Uchihara ,  Yasunori Usui ,  Hideyuki Ura

Inventor： Takeshi Uchihara ,  Yasunori Usui ,  Hideyuki Ura

IPC: H01L29/76

CPC classification number: H01L29/7838 ,  H01L29/417 ,  H03K17/941

Abstract: In various aspects, a MOSFET may include a semiconductor region of a first conductivity type; a first semiconductor region of a second conductivity type provided in the semiconductor region; a second semiconductor region of the first conductivity type provided in the semiconductor region, the second semiconductor region having a higher impurity concentration than the semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region; a fourth semiconductor region of the second conductivity type configured to be contact with the first semiconductor region and the third semiconductor region, the fourth semiconductor region having a lower impurity concentration than the first semiconductor region and the third semiconductor region; a gate electrode provided on the fourth semiconductor region via a gate insulating layer, an edge of the gate electrode spaced from a junction between the first semiconductor region and the fourth semiconductor region.

Abstract translation: 在各个方面，MOSFET可以包括第一导电类型的半导体区域; 设置在半导体区域中的第二导电类型的第一半导体区域; 设置在所述半导体区域中的所述第一导电类型的第二半导体区域，所述第二半导体区域具有比所述半导体区域更高的杂质浓度; 设置在第二半导体区域上的第二导电类型的第三半导体区域; 第二导电类型的第四半导体区域被配置为与第一半导体区域和第三半导体区域接触，第四半导体区域具有比第一半导体区域和第三半导体区域低的杂质浓度; 栅极，经由栅极绝缘层设置在第四半导体区域上，栅电极的边缘与第一半导体区域和第四半导体区域之间的接合部分间隔开。

公开(公告)号：US06943406B2

公开(公告)日：2005-09-13

申请号：US10697994

申请日：2003-10-30

Applicant: Takeshi Uchihara ,  Yasunori Usui ,  Hideyuki Ura ,  Takuma Hara

Inventor： Takeshi Uchihara ,  Yasunori Usui ,  Hideyuki Ura ,  Takuma Hara

IPC: H01L21/336 ,  H01L21/332 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/113

CPC classification number: H01L29/513 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/518 ,  H01L29/7835 ,  H01L29/78624

Abstract: According to the present invention, there is provided a semiconductor device having, a semiconductor substrate having a surface on which an insulating layer is formed, a first-conductivity-type first semiconductor layer formed on the insulating layer and having a first impurity concentration, a first-conductivity-type second semiconductor region formed in the first semiconductor layer from a surface of the first semiconductor layer to a surface of the insulating layer, and having a concentration higher than the first impurity concentration, a second-conductivity-type third semiconductor region formed in the first semiconductor layer from the surface of the first semiconductor layer to the surface of the insulating layer with a predetermined distance between the second and third semiconductor regions, and having a second impurity concentration, a second-conductivity-type fourth semiconductor region formed in a surface portion of the second semiconductor region, and having a concentration higher than the second impurity concentration, an insulating film formed over the surfaces of the first, second, third, and fourth semiconductor layers, and a control electrode formed on the insulating film, wherein a junction of first and second conductivity types formed between the first semiconductor layer and the third semiconductor region is positioned below the control electrode, or below an end portion, on a side of the third semiconductor region, of the control electrode, via the insulating film.

Abstract translation: 根据本发明，提供了一种半导体器件，具有：具有形成有绝缘层的表面的半导体衬底，形成在绝缘层上并具有第一杂质浓度的第一导电型第一半导体层， 第一导电型第二半导体区域，形成在第一半导体层中，从第一半导体层的表面到绝缘层的表面，并且具有比第一杂质浓度高的浓度;第二导电型第三半导体区域 在所述第一半导体层中形成有从所述第一半导体层的表面到所述绝缘层的表面的第二和第三半导体区域之间的预定距离，并且具有第二杂质浓度，形成第二导电型第四半导体区域 在第二半导体区域的表面部分中，并且具有集中 n高于第二杂质浓度，形成在第一，第二，第三和第四半导体层的表面上的绝缘膜和形成在绝缘膜上的控制电极，其中形成在第一和第二半导体层之间的第一和第二导电类型的接合 第一半导体层和第三半导体区域经由绝缘膜位于控制电极的第三半导体区域的一侧上的控制电极的下方或下方的端部下方。

公开(公告)号：US07537983B2

公开(公告)日：2009-05-26

申请号：US11344178

申请日：2006-02-01

Applicant: Takeshi Uchihara ,  Yasunori Usui ,  Akira Tanioka ,  Takuma Hara

Inventor： Takeshi Uchihara ,  Yasunori Usui ,  Akira Tanioka ,  Takuma Hara

IPC: H01L21/84 ,  H01L21/8234

CPC classification number: H01L29/7835 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7836 ,  H01L29/78624

Abstract: In various aspects, a MOSFET may include an active region of a first conductivity type provided on an insulating layer, the active region having a first portion and a second portion, the first portion being thicker than the second portion; a base region of the first conductivity type provided on the insulating layer, the base region having a higher impurity concentration than the first portion of the active region, the base region being in contact with the first portion of the active region and the insulating layer; a drain region of a second conductivity type provided on the insulating layer, the drain region being in contact with the second portion of the active region and the insulating layer, the drain region being spaced from the base region; a source region of the second conductivity type provided on a surface of the base region; a gate insulating layer provided on the source region, the base region, the active region and the drain region; and a gate electrode provided on the gate insulating layer.

Abstract translation: 在各个方面，MOSFET可以包括提供在绝缘层上的第一导电类型的有源区，该有源区具有第一部分和第二部分，第一部分比第二部分厚; 所述第一导电类型的基极区域设置在所述绝缘层上，所述基极区域具有比所述有源区域的第一部分高的杂质浓度，所述基极区域与所述有源区域的第一部分和所述绝缘层接触; 设置在所述绝缘层上的第二导电类型的漏极区域，所述漏极区域与所述有源区域的第二部分和所述绝缘层接触，所述漏极区域与所述基极区域间隔开; 设置在所述基底区域的表面上的所述第二导电类型的源极区域; 设置在源极区域，基极区域，有源区域和漏极区域上的栅极绝缘层; 以及设置在栅极绝缘层上的栅电极。

公开(公告)号：US20060197112A1

公开(公告)日：2006-09-07

申请号：US11275020

申请日：2005-12-02

Applicant: Takeshi Uchihara ,  Yasunori Usui ,  Takashi Nishimura

Inventor： Takeshi Uchihara ,  Yasunori Usui ,  Takashi Nishimura

IPC: H01L29/76

CPC classification number: H01L31/12 ,  H03K17/78 ,  H03K17/785

Abstract: In various aspects, an optical coupling device may include a light emitting element configured to emit an optical signal; a photo receiving element having a serial connected of photo diodes, the photo receiving element configured to receive the optical signal and generate an electrical signal; and a control circuit having an active element, a source and a drain of the active element connected to both ends of the photo receiving element; wherein the breakdown voltage of the control circuit is no more than an open circuit voltage of the photo receiving element.

Abstract translation: 在各个方面，光耦合装置可以包括被配置为发射光信号的发光元件; 光接收元件，其具有光电二极管的串联连接，所述光接收元件被配置为接收所述光信号并产生电信号; 以及控制电路，其具有有源元件，所述有源元件的源极和漏极连接到所述光接收元件的两端; 其中所述控制电路的击穿电压不超过所述光接收元件的开路电压。

公开(公告)号：US20060170049A1

公开(公告)日：2006-08-03

申请号：US11344178

申请日：2006-02-01

Applicant: Takeshi Uchihara ,  Yasunori Usui ,  Akira Tanioka ,  Takuma Hara

Inventor： Takeshi Uchihara ,  Yasunori Usui ,  Akira Tanioka ,  Takuma Hara

IPC: H01L27/12

CPC classification number: H01L29/7835 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7836 ,  H01L29/78624

Abstract: In various aspects, a MOSFET may include an active region of a first conductivity type provided on an insulating layer, the active region having a first portion and a second portion, the first portion being thicker than the second portion; a base region of the first conductivity type provided on the insulating layer, the base region having a higher impurity concentration than the first portion of the active region, the base region being in contact with the first portion of the active region and the insulating layer; a drain region of a second conductivity type provided on the insulating layer, the drain region being in contact with the second portion of the active region and the insulating layer, the drain region being spaced from the base region; a source region of the second conductivity type provided on a surface of the base region; a gate insulating layer provided on the source region, the base region, the active region and the drain region; and a gate electrode provided on the gate insulating layer.

公开(公告)号：US5336907A

公开(公告)日：1994-08-09

申请号：US969491

申请日：1992-10-30

Applicant: Hidetoshi Nakanishi ,  Yasunori Usui

Inventor： Hidetoshi Nakanishi ,  Yasunori Usui

IPC: H01L29/745 ,  H01L29/749 ,  H01L29/74 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/749 ,  H01L29/7455

Abstract: A gate electrode includes a first region formed in an OFF gate region and a second region formed in an ON gate region. A P-channel region is formed in the OFF gate region and an N-channel region is formed in the ON gate region to separate these gate regions. Since a P.sup.- -type channel region of low impurity concentration is formed at an end of a P-type base region in which the N-channel region is formed, the impurity concentration of the P-type base region can be increased and thus turn-off characteristic is improved.

Abstract translation: 栅极电极包括形成在OFF栅极区域中的第一区域和形成在ON栅极区域中的第二区域。 在OFF栅极区域中形成P沟道区，并且在导通栅极区域中形成N沟道区以分离这些栅极区。 由于在形成有N沟道区的P型基极区的端部形成有低杂质浓度的P型沟道区，因此能够提高P型基极区域的杂质浓度， 改进了特性。

公开(公告)号：US4717947A

公开(公告)日：1988-01-05

申请号：US675150

申请日：1984-11-27

Applicant: Hideo Matsuda ,  Yoshiaki Tsunoda ,  Takashi Fujiwara ,  Yasunori Usui

Inventor： Hideo Matsuda ,  Yoshiaki Tsunoda ,  Takashi Fujiwara ,  Yasunori Usui

IPC: H01L31/10 ,  H01L29/74 ,  H01L29/744 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111 ,  H01L27/02 ,  H01L27/14 ,  H01L29/78

CPC classification number: H01L31/1113 ,  H01L29/74 ,  H01L29/7455

Abstract: A semiconductor device has a main GTO thyristor section, an auxiliary GTO thyristor section and a MOS transistor section. The main GTO thyristor section is turned on and off in accordance with a gate signal supplied to its gate terminal. The auxiliary GTO thyristor section supplies an igniting signal to the gate of the main GTO thyristor in accordance with an optical signal. The MOS transistor supplies an extinguishing signal to the gate of the main GTO thyristor section in accordance with an optical signal supplied to it.

Abstract translation: 半导体器件具有主GTO晶闸管部分，辅助GTO晶闸管部分和MOS晶体管部分。 主GTO晶闸管部分根据提供给其栅极端子的栅极信号而导通和截止。 辅助GTO晶闸管部分根据光信号向主GTO晶闸管的栅极提供点火信号。 MOS晶体管根据提供给其的光信号向主GTO晶闸管部分的栅极提供熄灭信号。

公开(公告)号：US20120165081A1

公开(公告)日：2012-06-28

申请号：US13331226

申请日：2011-12-20

Applicant: Youichi USHIGOME ,  Satoshi Ogasawara ,  Hiromasu Meguro ,  Yasunori Usui

Inventor： Youichi USHIGOME ,  Satoshi Ogasawara ,  Hiromasu Meguro ,  Yasunori Usui

IPC: H04M1/00

CPC classification number: H04M1/0252 ,  G06F1/1656 ,  H04M1/0249

Abstract: A mobile device of the present invention having an upper case, a lower case arranged under the upper case, and a middle case arranged inside the upper case and the lower case, includes a first engaging section which is provided in the peripheral edge portion of the undersurface of the upper case, a second engaging section which is provided in the peripheral edge portion of the top surface of the middle case and engages with the first engaging section, a third engaging section which is provided in the peripheral edge portion of the undersurface of the middle case, and a fourth engaging section which is provided in the peripheral edge portion of the top surface of the lower case and engages with the third engaging section.

Abstract translation: 本发明的移动装置具有设置在上壳体和下壳体内的上壳体，下壳体和设置在上壳体内的中间壳体的移动装置，包括：第一接合部，其设置在上壳体的周缘部 上壳体的下表面，设置在中间壳体的上表面的周缘部分中并与第一接合部分接合的第二接合部分，第三接合部分设置在第二接合部分的下表面的周边部分中 中间壳体和第四接合部分，其设置在下壳体的顶表面的周缘部分中并与第三接合部分接合。

公开(公告)号：US5543639A

公开(公告)日：1996-08-06

申请号：US138434

申请日：1993-10-08

Applicant: Hidetoshi Nakanishi ,  Yasunori Usui ,  Shigenori Yakushiji

Inventor： Hidetoshi Nakanishi ,  Yasunori Usui ,  Shigenori Yakushiji

IPC: H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC classification number: H01L29/7455 ,  H01L29/749

Abstract: On one major surface of an n.sup.- -type semiconductor substrate, a p-type base region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

Abstract translation: 在n型半导体衬底的一个主表面上，在半导体衬底中形成p型基极区域，在p型基极区域形成n型发射极区域。 在p型基极区附近形成p型源区。 阴极具有所谓的短路发射极结构，其中阴极连接到p型源极区，p型基极区和n型发射极区。 p型源区优选具有与p型基极区相邻的图案。 p型基区优选由彼此电连接的多个扩散层构成。 因此，可以提高器件的关断特性，并且在不降低关断特性的情况下提高导通特性，从而改善导通特性与关断特性之间的折衷。

公开(公告)号：US4918514A

公开(公告)日：1990-04-17

申请号：US173458

申请日：1988-03-25

Applicant: Hideo Matsuda ,  Yasunori Usui ,  Shinjiro Kojima ,  Masaru Ando

Inventor： Hideo Matsuda ,  Yasunori Usui ,  Shinjiro Kojima ,  Masaru Ando

IPC: H01L21/52 ,  H01L23/051 ,  H01L23/48

CPC classification number: H01L23/051 ,  H01L24/72 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/1301

Abstract: A soft metal plate having substantially equal hardness as emitter electrodes formed of soft metal is disposed between the emitter electrodes and a heat buffer metal plate formed of hard metal, and pressure applied to the emitter electrodes is shared by the soft metal plate, so as to reduce the thermal fatigue of the emitter electrodes.