公开(公告)号：US20060170041A1

公开(公告)日：2006-08-03

申请号：US11335602

申请日：2006-01-20

Applicant: Takeshi Uchihara ,  Yasunori Usui ,  Hideyuki Ura

Inventor： Takeshi Uchihara ,  Yasunori Usui ,  Hideyuki Ura

IPC: H01L29/76

CPC classification number: H01L29/7838 ,  H01L29/417 ,  H03K17/941

Abstract: In various aspects, a MOSFET may include a semiconductor region of a first conductivity type; a first semiconductor region of a second conductivity type provided in the semiconductor region; a second semiconductor region of the first conductivity type provided in the semiconductor region, the second semiconductor region having a higher impurity concentration than the semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region; a fourth semiconductor region of the second conductivity type configured to be contact with the first semiconductor region and the third semiconductor region, the fourth semiconductor region having a lower impurity concentration than the first semiconductor region and the third semiconductor region; a gate electrode provided on the fourth semiconductor region via a gate insulating layer, an edge of the gate electrode spaced from a junction between the first semiconductor region and the fourth semiconductor region.

Abstract translation: 在各个方面，MOSFET可以包括第一导电类型的半导体区域; 设置在半导体区域中的第二导电类型的第一半导体区域; 设置在所述半导体区域中的所述第一导电类型的第二半导体区域，所述第二半导体区域具有比所述半导体区域更高的杂质浓度; 设置在第二半导体区域上的第二导电类型的第三半导体区域; 第二导电类型的第四半导体区域被配置为与第一半导体区域和第三半导体区域接触，第四半导体区域具有比第一半导体区域和第三半导体区域低的杂质浓度; 栅极，经由栅极绝缘层设置在第四半导体区域上，栅电极的边缘与第一半导体区域和第四半导体区域之间的接合部分间隔开。

公开(公告)号：US06943406B2

公开(公告)日：2005-09-13

申请号：US10697994

申请日：2003-10-30

Applicant: Takeshi Uchihara ,  Yasunori Usui ,  Hideyuki Ura ,  Takuma Hara

Inventor： Takeshi Uchihara ,  Yasunori Usui ,  Hideyuki Ura ,  Takuma Hara

IPC: H01L21/336 ,  H01L21/332 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/113

CPC classification number: H01L29/513 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/511 ,  H01L29/518 ,  H01L29/7835 ,  H01L29/78624

Abstract: According to the present invention, there is provided a semiconductor device having, a semiconductor substrate having a surface on which an insulating layer is formed, a first-conductivity-type first semiconductor layer formed on the insulating layer and having a first impurity concentration, a first-conductivity-type second semiconductor region formed in the first semiconductor layer from a surface of the first semiconductor layer to a surface of the insulating layer, and having a concentration higher than the first impurity concentration, a second-conductivity-type third semiconductor region formed in the first semiconductor layer from the surface of the first semiconductor layer to the surface of the insulating layer with a predetermined distance between the second and third semiconductor regions, and having a second impurity concentration, a second-conductivity-type fourth semiconductor region formed in a surface portion of the second semiconductor region, and having a concentration higher than the second impurity concentration, an insulating film formed over the surfaces of the first, second, third, and fourth semiconductor layers, and a control electrode formed on the insulating film, wherein a junction of first and second conductivity types formed between the first semiconductor layer and the third semiconductor region is positioned below the control electrode, or below an end portion, on a side of the third semiconductor region, of the control electrode, via the insulating film.

Abstract translation: 根据本发明，提供了一种半导体器件，具有：具有形成有绝缘层的表面的半导体衬底，形成在绝缘层上并具有第一杂质浓度的第一导电型第一半导体层， 第一导电型第二半导体区域，形成在第一半导体层中，从第一半导体层的表面到绝缘层的表面，并且具有比第一杂质浓度高的浓度;第二导电型第三半导体区域 在所述第一半导体层中形成有从所述第一半导体层的表面到所述绝缘层的表面的第二和第三半导体区域之间的预定距离，并且具有第二杂质浓度，形成第二导电型第四半导体区域 在第二半导体区域的表面部分中，并且具有集中 n高于第二杂质浓度，形成在第一，第二，第三和第四半导体层的表面上的绝缘膜和形成在绝缘膜上的控制电极，其中形成在第一和第二半导体层之间的第一和第二导电类型的接合 第一半导体层和第三半导体区域经由绝缘膜位于控制电极的第三半导体区域的一侧上的控制电极的下方或下方的端部下方。

公开(公告)号：US20110140197A1

公开(公告)日：2011-06-16

申请号：US12886449

申请日：2010-09-20

Applicant: Kouta Tomita ,  Noboru Matsuda ,  Hideyuki Ura

Inventor： Kouta Tomita ,  Noboru Matsuda ,  Hideyuki Ura

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, first trenches, a second trench, an insulating film, a gate electrode, a first main electrode, a second main electrode, a channel stopper layer and a channel stopper electrode. The second semiconductor layer of the first conductivity type is provided on the first semiconductor layer. The third semiconductor layer of a second conductivity type is provided on the second semiconductor layer. The fourth semiconductor layer of the first conductivity type is provided on the third semiconductor layer. The gate electrode is provided in the first trenches via the insulating film. The first main electrode is provided on the first semiconductor layer. The second main electrode is provided to contact the element part. The channel stopper electrode is provided on the termination part.

Abstract translation: 根据一个实施例，半导体器件包括第一导电类型的第一半导体层，第二半导体层，第三半导体层，第四半导体层，第一沟槽，第二沟槽，绝缘膜，栅电极， 第一主电极，第二主电极，沟道阻挡层和通道阻挡电极。 第一导电类型的第二半导体层设置在第一半导体层上。 第二导电类型的第三半导体层设置在第二半导体层上。 第一导电类型的第四半导体层设置在第三半导体层上。 栅电极经由绝缘膜设置在第一沟槽中。 第一主电极设置在第一半导体层上。 第二主电极设置成与元件部分接触。 通道阻挡电极设置在终端部分上。

公开(公告)号：US08299523B2

公开(公告)日：2012-10-30

申请号：US13195579

申请日：2011-08-01

Applicant: Kouta Tomita ,  Noboru Matsuda ,  Hideyuki Ura

Inventor： Kouta Tomita ,  Noboru Matsuda ,  Hideyuki Ura

IPC: H01L29/76 ,  H01L31/062

CPC classification number: H01L29/7813 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/7811

Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.

Abstract translation: 通常，根据一个实施例，半导体器件包括第一电极，第一导电类型的第一和第二半导体层，第二导电类型的第三半导体层，第一导电类型的第四半导体层，第一导电类型的第四半导体层 订购。 器件区域包括位于第一沟槽内的栅电极。 具有环形结构的第二沟槽形成穿过第四和第三半导体层的第一区域到第二半导体层，并且包括内部的器件区域和围绕第一区域的第二区域。 第一开口设置在相邻的第一沟槽之间。 具有比第一开口宽的宽度的第二开口设置在装置区域外的第一区域中。 第二电极通过第一和第二开口电连接到第三和第四半导体层。

公开(公告)号：US08269272B2

公开(公告)日：2012-09-18

申请号：US12886449

申请日：2010-09-20

Applicant: Kouta Tomita ,  Noboru Matsuda ,  Hideyuki Ura

Inventor： Kouta Tomita ,  Noboru Matsuda ,  Hideyuki Ura

IPC: H01L29/76 ,  H01L31/062

CPC classification number: H01L29/7811 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, first trenches, a second trench, an insulating film, a gate electrode, a first main electrode, a second main electrode, a channel stopper layer and a channel stopper electrode. The second semiconductor layer of the first conductivity type is provided on the first semiconductor layer. The third semiconductor layer of a second conductivity type is provided on the second semiconductor layer. The fourth semiconductor layer of the first conductivity type is provided on the third semiconductor layer. The gate electrode is provided in the first trenches via the insulating film. The first main electrode is provided on the first semiconductor layer. The second main electrode is provided to contact the element part. The channel stopper electrode is provided on the termination part.

Abstract translation: 根据一个实施例，半导体器件包括第一导电类型的第一半导体层，第二半导体层，第三半导体层，第四半导体层，第一沟槽，第二沟槽，绝缘膜，栅电极， 第一主电极，第二主电极，沟道阻挡层和通道阻挡电极。 第一导电类型的第二半导体层设置在第一半导体层上。 第二导电类型的第三半导体层设置在第二半导体层上。 第一导电类型的第四半导体层设置在第三半导体层上。 栅电极经由绝缘膜设置在第一沟槽中。 第一主电极设置在第一半导体层上。 第二主电极设置成与元件部分接触。 通道阻挡电极设置在终端部分上。