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    Systems and methods for die-to-die communication
    2.
    发明授权
    Systems and methods for die-to-die communication 有权

    公开(公告)号：US11509346B2

    公开(公告)日：2022-11-22

    申请号：US17378956

    申请日：2021-07-19

    申请人： Taiwan Semiconductor Manufacturing Company Limited

    发明人： Huan-Neng Chen ,  Chewn-Pu Jou ,  Feng-Wei Kuo ,  Lan-Chou Cho ,  William Wu Shen

    IPC分类号： H04B1/40 ,  H04B1/00 ,  H04L1/00 ,  H04L1/18 ,  H04L27/00

    摘要： A transceiver disposed on a first die in a bidirectional differential die-to-die communication system is disclosed. The transceiver includes a transmission section configured to modulate a first data onto a carrier signal having a first frequency for transmission via a bidirectional differential transmission line; and a reception section configured to receive signals from the bidirectional differential transmission line, the reception section including a filter configured to pass frequencies within a first passband that includes a second frequency, the first frequency being outside of the first passband. According to some embodiments, the reception section is configured to receive, via the bidirectional differential transmission line, modulated data at the second frequency at a same time that the transmission section transmits the modulated data at the first frequency.

    Integrated fan-out package with 3D magnetic core inductor
    3.
    发明授权
    Integrated fan-out package with 3D magnetic core inductor 有权

    公开(公告)号：US10923417B2

    公开(公告)日：2021-02-16

    申请号：US15897272

    申请日：2018-02-15

    申请人： Taiwan Semiconductor Manufacturing Company Limited

    发明人： Wen-Shiang Liao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Chewn-Pu Jou ,  Feng Wei Kuo

    IPC分类号： H01L23/31 ,  H01L23/522 ,  H01L49/02 ,  H01L23/00 ,  H01L21/683 ,  H01L23/64 ,  H01L23/66

    摘要： Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

    MiM capacitor
    8.
    发明授权
    MiM capacitor 有权
    MiM电容

    公开(公告)号：US09502886B2

    公开(公告)日：2016-11-22

    申请号：US14046951

    申请日：2013-10-05

    申请人： Taiwan Semiconductor Manufacturing Company Limited

    发明人： Chien-Jung Wang ,  Huan-Neng Chen ,  Chewn-Pu Jou ,  Chwei-Ching Chiu

    IPC分类号： H01H35/00 ,  H01H83/00 ,  H02H7/16

    CPC分类号： H02H7/16 ,  Y10T307/766

    摘要： One or more systems and techniques for managing one or more electronic devices are provided. A determination is made that a first capacitor in a set of one or more capacitors has a defect. Responsive to the determination, the first capacitor is disabled, and a second capacitor is enabled.

    摘要翻译： 提供了一种或多种用于管理一个或多个电子设备的系统和技术。 确定一组或多个电容器中的第一电容器具有缺陷。 响应于确定，第一电容器被禁用，并且第二电容器被使能。

    Phase-locked loop (PLL)
    9.
    发明授权
    Phase-locked loop (PLL) 有权
    锁相环（PLL）

    公开(公告)号：US09385731B2

    公开(公告)日：2016-07-05

    申请号：US14332548

    申请日：2014-07-16

    申请人： Taiwan Semiconductor Manufacturing Company Limited

    发明人： Feng Wei Kuo ,  Kuang-Kai Yen ,  Huan-Neng Chen ,  Lee Tsung Hsiung ,  Chewn-Pu Jou ,  Robert Bogdan Staszewski

    IPC分类号： H03L7/06 ,  H03L7/093 ,  H03L7/095

    CPC分类号： H03L7/093 ,  H03L7/095 ,  H03L2207/50

    摘要： A phase-locked loop (PLL) is provided. The PLL comprises a clock adjuster configured to receive an initial clock signal having an initial frequency and a mode control signal. The clock adjuster is configured to modify the initial clock signal into a modified clock signal based on the mode control signal. The PLL is configured such that a loop bandwidth is equal to a specified bandwidth. When the modified clock signal is changed, a loop gain of a loop filter is adjusted such that the loop bandwidth is substantially equal to the specified bandwidth. When the modified clock signal is changed, an oscillator tuning word (OTW) signal is modified into a normalized OTW signal such that the loop bandwidth is substantially equal to the specified bandwidth.

    摘要翻译： 提供锁相环（PLL）。 PLL包括被配置为接收具有初始频率和模式控制信号的初始时钟信号的时钟调整器。 时钟调整器被配置为基于模式控制信号将初始时钟信号修改为修改的时钟信号。 PLL被配置为使得环路带宽等于指定的带宽。 当修改的时钟信号改变时，调整环路滤波器的环路增益，使得环路带宽基本上等于指定的带宽。 当修改的时钟信号改变时，振荡器调谐字（OTW）信号被修改为归一化OTW信号，使得环路带宽基本上等于指定的带宽。