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公开(公告)号:US20150228577A1
公开(公告)日:2015-08-13
申请号:US14178422
申请日:2014-02-12
发明人: Chung-Hao Tsai , Jeng-Shien Hsieh , Chuei-Tang Wang , Chen-Hua Yu
IPC分类号: H01L23/522 , H01L21/768
CPC分类号: H01L23/5228 , H01L23/5222 , H01L23/66 , H01L2223/6672 , H01L2924/0002 , H01L2924/00
摘要: One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement includes a power divider comprising a transmission line and a resistor, where the transmission line is over and connected to an active area input, a first active area output and a second active area output. The semiconductor arrangement has a smaller chip size than a semiconductor arrangement where the transmission line is not over the active area input, the first active area output and the second active area output. The smaller chip size is due to the active area input, the first active area output and the second active area output being formed closer to one another than would be possible in a semiconductor arrangement where the transmission line is formed between at least one of the active area input, the first active area output or the second active area output.
摘要翻译: 本文提供了一种或多种用于形成半导体布置及由此形成的结构结构的技术。 半导体装置包括功率分配器,其包括传输线和电阻器,其中传输线路结束并连接到有源区域输入端,第一有源区域输出端和第二有源区域输出端。 半导体布置具有比半导体布置小的芯片尺寸,其中传输线不在有源区输入,第一有源区输出和第二有源区输出之上。 较小的芯片尺寸是由于有源区域输入,第一有源区域输出和第二有源区域输出形成为比半导体布置更接近地形成,其中传输线形成在活动区域中的至少一个之间 区域输入,第一有源区输出或第二有源区输出。
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公开(公告)号:US20140253262A1
公开(公告)日:2014-09-11
申请号:US13788537
申请日:2013-03-07
发明人: Jeng-Shien Hsieh , Monsen Liu , Chung-Hao Tsai , Lai Wei Chih , Yeh En-Hsiang , Chuei-Tang Wang , Chen-Hua Yu
IPC分类号: H01P3/08
CPC分类号: H01P1/2007 , H01L23/5223 , H01L23/5227 , H01L23/528 , H01L23/64 , H01L23/66 , H01L2924/0002 , H03H7/0138 , H03H2001/0092 , Y10T29/49117 , H01L2924/00
摘要: Among other things, one or more techniques and systems for selectively filtering RF signals within one or more RF frequency band are provided. In particular, an RF choke, such as a 3D RF choke or a semi-lumped RF choke, configured to selectively filter such RF signals is provided. The RF choke comprises a metal connection line configured as an inductive element for the RF choke. In an example, one or more metal lines, such as a metal open stub, are formed as capacitive elements for the RF choke. In another example, one or more through vias are formed as capacitive elements for the RF choke. In this way, the RF choke allows DC power signals to pass through the metal connection line, while impeding RF signals within the one or more RF frequency bands from passing through the metal connection line.
摘要翻译: 除其他之外,还提供了一个或多个用于选择性地过滤一个或多个RF频带内的RF信号的技术和系统。 特别地,提供了被配置为选择性地滤波这样的RF信号的RF扼流圈,例如3D RF扼流圈或半集总RF扼流圈。 RF扼流器包括配置为用于RF扼流圈的电感元件的金属连接线。 在一个示例中,形成一个或多个金属线,例如金属开路短截线,作为RF扼流圈的电容元件。 在另一示例中,一个或多个通孔形成为RF扼流圈的电容元件。 以这种方式,RF扼流圈允许DC功率信号通过金属连接线,同时阻止一个或多个RF频带内的RF信号通过金属连接线。
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公开(公告)号:US09331018B2
公开(公告)日:2016-05-03
申请号:US14178422
申请日:2014-02-12
发明人: Chung-Hao Tsai , Jeng-Shien Hsieh , Chuei-Tang Wang , Chen-Hua Yu
IPC分类号: H01L27/10 , H01L23/522 , H01L21/768
CPC分类号: H01L23/5228 , H01L23/5222 , H01L23/66 , H01L2223/6672 , H01L2924/0002 , H01L2924/00
摘要: One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement includes a power divider comprising a transmission line and a resistor, where the transmission line is over and connected to an active area input, a first active area output and a second active area output. The semiconductor arrangement has a smaller chip size than a semiconductor arrangement where the transmission line is not over the active area input, the first active area output and the second active area output. The smaller chip size is due to the active area input, the first active area output and the second active area output being formed closer to one another than would be possible in a semiconductor arrangement where the transmission line is formed between at least one of the active area input, the first active area output or the second active area output.
摘要翻译: 本文提供了一种或多种用于形成半导体布置及由此形成的结构结构的技术。 半导体装置包括功率分配器,其包括传输线和电阻器,其中传输线路结束并连接到有源区域输入端,第一有源区域输出端和第二有源区域输出端。 半导体布置具有比半导体布置小的芯片尺寸,其中传输线不在有源区输入,第一有源区输出和第二有源区输出之上。 较小的芯片尺寸是由于有源区域输入,第一有源区域输出和第二有源区域输出形成为比半导体布置更接近地形成,其中传输线形成在活动区域中的至少一个之间 区域输入,第一有源区输出或第二有源区输出。
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公开(公告)号:US20230420437A1
公开(公告)日:2023-12-28
申请号:US17847335
申请日:2022-06-23
发明人: Chieh-Yen Chen , Jeng-Shien Hsieh , Chuei-Tang Wang , Chen-Hua Yu
IPC分类号: H01L25/18 , H01L25/065 , H01L23/00 , H01L25/00 , H01L21/768
CPC分类号: H01L25/18 , H01L25/0657 , H01L24/92 , H01L25/50 , H01L24/83 , H01L21/76898 , H01L2225/06524 , H01L2225/06544 , H01L2225/06565 , H01L24/29 , H01L2224/29186 , H01L2924/05442 , H01L24/32 , H01L2224/32 , H01L24/08 , H01L2224/08145 , H01L2224/9222 , H01L24/02 , H01L2224/02372 , H01L2224/05647 , H01L2224/05639 , H01L2224/05671 , H01L2224/05655 , H01L2224/05611 , H01L2224/05684 , H01L2224/05666 , H01L2224/05644 , H01L24/80 , H01L2224/80203 , H01L2224/8083 , H01L2224/80379 , H01L2924/0665 , H01L2924/07025 , H01L2924/06 , H01L2224/8085 , H01L2224/8089 , H01L2224/80905 , H01L2224/83203 , H01L2224/83931 , H01L2224/8389 , H01L2924/1431 , H01L2924/1432 , H01L2924/1433 , H01L2924/1434
摘要: A semiconductor structure, includes a logic die, a memory die stack bonded to the logic die by a first oxide bond, and including a first pair of memory dies bonded together by a first direct bond, and a first through silicon via (TSV) in the logic die and extending across the first oxide bond and electrically connecting the logic die to the first pair of memory dies.
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公开(公告)号:US09773730B2
公开(公告)日:2017-09-26
申请号:US14991072
申请日:2016-01-08
发明人: Chung-Hao Tsai , Jeng-Shien Hsieh , Chuei-Tang Wang , Chen-Hua Yu
IPC分类号: H01L23/00 , H01L23/522 , H01L23/66
CPC分类号: H01L23/5228 , H01L23/5222 , H01L23/66 , H01L2223/6672 , H01L2924/0002 , H01L2924/00
摘要: One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement includes a power divider comprising a transmission line and a resistor, where the transmission line is over and connected to an active area input, a first active area output and a second active area output. The semiconductor arrangement has a smaller chip size than a semiconductor arrangement where the transmission line is not over the active area input, the first active area output and the second active area output. The smaller chip size is due to the active area input, the first active area output and the second active area output being formed closer to one another than would be possible in a semiconductor arrangement where the transmission line is formed between at least one of the active area input, the first active area output or the second active area output.
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公开(公告)号:US09761553B2
公开(公告)日:2017-09-12
申请号:US13655695
申请日:2012-10-19
发明人: Chewn-Pu Jou , Chuei-Tang Wang , Fu-Lung Hsueh
IPC分类号: H01F5/00 , H01F27/28 , H01F27/29 , H01F17/06 , H01L27/08 , H01L25/00 , H01L23/00 , H01L23/64 , H01L25/16 , H01F17/00 , H01F41/04 , H01L23/31
CPC分类号: H01L24/18 , H01F17/0033 , H01F41/046 , H01L23/3128 , H01L23/645 , H01L24/20 , H01L25/16 , H01L2224/04105 , H01L2224/12105 , H01L2224/24195 , H01L2924/14 , H01L2924/19042 , H01L2924/19105 , H01L2924/30107 , Y10T29/4902
摘要: Among other things, an inductor comprising a conductive trace and a method for forming the inductor are provided. The inductor comprises a magnetic structure, such as a ferrite core. A molding material, such as a dielectric, is formed around the magnetic structure. A conductive trace, comprising one or more conductive pillars interconnected by one or more upper interconnects and one or more lower interconnects, is formed around the magnetic structure to form the inductor. The conductive trace allows physical limitations associated with winding a wire to be avoided, and thus allows the inductor to be smaller than wire wound inductors. In one example, the inductor is formed within an integrated circuit package comprising an active device, such as an integrated circuit. In this way, the inductor can be connected to the integrated circuit within the integrated circuit package.
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公开(公告)号:US09391350B2
公开(公告)日:2016-07-12
申请号:US13788537
申请日:2013-03-07
发明人: Jeng-Shien Hsieh , Monsen Liu , Chung-Hao Tsai , Lai Wei Chih , Yeh En-Hsiang , Chuei-Tang Wang , Chen-Hua Yu
IPC分类号: H01P1/20 , H03H7/01 , H01L23/66 , H01L23/64 , H01L23/522 , H01L23/528 , H03H1/00
CPC分类号: H01P1/2007 , H01L23/5223 , H01L23/5227 , H01L23/528 , H01L23/64 , H01L23/66 , H01L2924/0002 , H03H7/0138 , H03H2001/0092 , Y10T29/49117 , H01L2924/00
摘要: Among other things, one or more techniques and systems for selectively filtering RF signals within one or more RF frequency band are provided. In particular, an RF choke, such as a 3D RF choke or a semi-lumped RF choke, configured to selectively filter such RF signals is provided. The RF choke comprises a metal connection line configured as an inductive element for the RF choke. In an example, one or more metal lines, such as a metal open stub, are formed as capacitive elements for the RF choke. In another example, one or more through vias are formed as capacitive elements for the RF choke. In this way, the RF choke allows DC power signals to pass through the metal connection line, while impeding RF signals within the one or more RF frequency bands from passing through the metal connection line.
摘要翻译: 除其他之外,还提供了一个或多个用于选择性地过滤一个或多个RF频带内的RF信号的技术和系统。 特别地,提供了被配置为选择性地滤波这样的RF信号的RF扼流圈,例如3D RF扼流圈或半集总RF扼流圈。 RF扼流器包括配置为用于RF扼流圈的电感元件的金属连接线。 在一个示例中,形成一个或多个金属线,例如金属开路短截线,作为RF扼流圈的电容元件。 在另一示例中,一个或多个通孔形成为RF扼流圈的电容元件。 以这种方式,RF扼流圈允许DC功率信号通过金属连接线,同时阻止一个或多个RF频带内的RF信号通过金属连接线。
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公开(公告)号:US20160126188A1
公开(公告)日:2016-05-05
申请号:US14991072
申请日:2016-01-08
发明人: Chung-Hao Tsai , Jeng-Shien Hsieh , Chuei-Tang Wang , Chen-Hua Yu
IPC分类号: H01L23/522 , H01L23/66
CPC分类号: H01L23/5228 , H01L23/5222 , H01L23/66 , H01L2223/6672 , H01L2924/0002 , H01L2924/00
摘要: One or more techniques for forming a semiconductor arrangement and resulting structures formed thereby are provided herein. The semiconductor arrangement includes a power divider comprising a transmission line and a resistor, where the transmission line is over and connected to an active area input, a first active area output and a second active area output. The semiconductor arrangement has a smaller chip size than a semiconductor arrangement where the transmission line is not over the active area input, the first active area output and the second active area output. The smaller chip size is due to the active area input, the first active area output and the second active area output being formed closer to one another than would be possible in a semiconductor arrangement where the transmission line is formed between at least one of the active area input, the first active area output or the second active area output.
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公开(公告)号:US20150371772A1
公开(公告)日:2015-12-24
申请号:US14840410
申请日:2015-08-31
发明人: Chewn-Pu Jou , Chuei-Tang Wang , Fu-Lung Hsueh
IPC分类号: H01F41/02
CPC分类号: H01L24/19 , H01F17/0033 , H01F41/046 , H01L23/3128 , H01L23/645 , H01L25/16 , H01L2224/12105 , H01L2224/24195 , H01L2924/14 , H01L2924/19042 , H01L2924/19105 , H01L2924/30107 , Y10T29/4902
摘要: Among other things, a method for forming an inductor is provided. The method includes forming an insulating layer on a carrier. The method includes forming a trench in the insulating layer. The method also includes forming a magnetic structure within the trench. The method includes forming a conductive trace around the magnetic structure to form the inductor.
摘要翻译: 其中,提供了形成电感器的方法。 该方法包括在载体上形成绝缘层。 该方法包括在绝缘层中形成沟槽。 该方法还包括在沟槽内形成磁结构。 该方法包括在磁性结构周围形成导电迹线以形成电感器。
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