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公开(公告)号：US09564488B2
公开(公告)日：2017-02-07
申请号：US14258832
申请日：2014-04-22
发明人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
IPC分类号： H01L29/10 , H01L21/762 , H01L29/78
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/7833 , H01L29/7843 , H01L29/7846
摘要： A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
摘要翻译： 提供了形成具有局部应力源的隔离沟槽的方法。 根据本发明的实施例，在衬底中形成沟槽并且部分地填充有电介质材料。 在一个实施例中，沟槽被填充有电介质层，并且执行平面化步骤以使其与衬底的表面平坦化。 然后将电介质材料凹入到衬底的表面下方。 在沟槽的凹陷部分中，电介质材料可以沿着侧壁保留，或者电介质材料可以沿侧壁去除。 然后可以在凹陷部分内的电介质材料上形成拉伸或压缩的应力膜。 应力膜也可以在晶体管或其它半导体结构上延伸。
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公开(公告)号：US08669153B2
公开(公告)日：2014-03-11
申请号：US13794621
申请日：2013-03-11
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.
摘要翻译： 提供了一种提供基板的方法， 在衬底中形成晶体管，晶体管具有虚拟栅极; 在衬底和晶体管上形成介电层; 在介电层中形成接触特征; 并且在形成接触特征之后，用金属栅极替换晶体管的虚拟栅极。 示例性接触特征是双重接触。
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公开(公告)号：US20130316504A1
公开(公告)日：2013-11-28
申请号：US13891921
申请日：2013-05-10
IPC分类号： H01L29/66
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。
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4.发明授权Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors 有权将I / O和核心MOS器件的形成与MOS电容器和电阻器集成公开(公告)号：US08728900B2
公开(公告)日：2014-05-20
申请号：US13649844
申请日：2012-10-11
IPC分类号： H01L21/20
CPC分类号： H01L27/0629 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L28/20 , H01L28/40 , H01L29/94
摘要： An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.
摘要翻译： 集成电路结构包括半导体衬底和第一和第二MOS器件。 第一MOS器件包括半导体衬底上的第一栅极电介质，其中第一栅极电介质是平面的; 以及位于第一栅极电介质上的第一栅电极。 第二MOS器件包括半导体衬底上的第二栅极电介质; 以及在所述第二栅极电介质上方的第二栅电极。 第二栅电极的高度大于第一栅电极的高度。 第二栅极电介质包括在第二栅电极下面的平面部分和在第二栅电极的侧壁上延伸的侧壁部分。
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公开(公告)号：US09455344B2
公开(公告)日：2016-09-27
申请号：US14284559
申请日：2014-05-22
IPC分类号： H01L29/66 , H01L29/78 , H01L21/28 , H01L29/423 , H01L29/49
CPC分类号： H01L29/78 , H01L21/28114 , H01L29/42376 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6659 , H01L29/66606 , H01L29/7833
摘要： A device having a gate where the profile of the gate provides a first width at a top region and a second width at a bottom region is described. The gate may include tapered sidewalls. The gate may be a metal gate structure.
摘要翻译： 描述了具有栅极的器件，其中栅极的轮廓在顶部区域提供第一宽度并且在底部区域提供第二宽度。 栅极可以包括锥形侧壁。 栅极可以是金属栅极结构。
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公开(公告)号：US20140030888A1
公开(公告)日：2014-01-30
申请号：US14046255
申请日：2013-10-04
IPC分类号： H01L21/768
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.
摘要翻译： 形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底上形成图案化特征，其中在所述图案化特征之间形成间隙; 用第一填充材料填充间隙，其中第一填充材料具有高于图案化特征的顶表面的第一顶表面; 以及执行第一平面化以降低所述第一填充材料的顶表面，直到所述图案化特征的顶表面露出。 该方法还包括沉积第二填充材料，其中第二填充材料具有高于图案化特征的顶表面的第二顶表面; 以及执行第二平面化以降低第二填充材料的顶表面，直到图案化特征的顶表面露出。
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公开(公告)号：US20130196496A1
公开(公告)日：2013-08-01
申请号：US13794621
申请日：2013-03-11
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/66
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.
摘要翻译： 提供了一种提供基板的方法， 在衬底中形成晶体管，晶体管具有虚拟栅极; 在衬底和晶体管上形成介电层; 在介电层中形成接触特征; 并且在形成接触特征之后，用金属栅极替换晶体管的虚拟栅极。 示例性接触特征是双重接触。
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8.发明授权SRAM devices utilizing strained-channel transistors and methods of manufacture 有权使用应变通道晶体管的SRAM器件和制造方法公开(公告)号：US09059310B2
公开(公告)日：2015-06-16
申请号：US14102289
申请日：2013-12-10
IPC分类号： H01L21/8238 , H01L27/11
CPC分类号： H01L21/8238 , H01L21/823864 , H01L27/11 , H01L27/1104
摘要： A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.
摘要翻译： 提供了一种新颖的SRAM存储单元结构及其制造方法。 SRAM存储单元结构包括形成在半导体衬底中的应变PMOS晶体管。 PMOS晶体管包括导致显着的PMOS晶体管驱动电流增加的外延生长的源极/漏极区域。 绝缘层形成在用于电隔离相邻PMOS晶体管的STI之上。 绝缘层基本上从半导体衬底表面升高。 升高的绝缘层有助于形成期望的厚的外延源/漏极区，并且由于在生长外延酸/漏区域的过程中由于外延层侧向延伸而防止相邻外延层之间的桥接。 形成升高的绝缘层的处理步骤与传统的CMOS工艺流程兼容。
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公开(公告)号：US08932951B2
公开(公告)日：2015-01-13
申请号：US14046255
申请日：2013-10-04
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/762
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.
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公开(公告)号：US20140242776A1
公开(公告)日：2014-08-28
申请号：US14258832
申请日：2014-04-22
发明人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/7833 , H01L29/7843 , H01L29/7846
摘要： A method of forming an isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
摘要翻译： 提供了形成具有局部应力源的隔离沟槽的方法。 根据本发明的实施例，在衬底中形成沟槽并且部分地填充有电介质材料。 在一个实施例中，沟槽被填充有电介质层，并且执行平面化步骤以使其与衬底的表面平坦化。 然后将电介质材料凹入到衬底的表面下方。 在沟槽的凹陷部分中，电介质材料可以沿着侧壁保留，或者电介质材料可以沿侧壁去除。 然后可以在凹陷部分内的电介质材料上形成拉伸或压缩的应力膜。 应力膜也可以在晶体管或其它半导体结构上延伸。
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