公开(公告)号：US11239154B2

公开(公告)日：2022-02-01

申请号：US14600619

申请日：2015-01-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chien-Ju Chao ,  Fang-Yu Fan ,  Yi-Chuin Tsai ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC分类号： H01L23/522 ,  H01L23/528 ,  G06F30/394

摘要： In some embodiments, a fishbone structure in a power network includes a first conductive segment in a first conductive layer running in a first direction, a plurality of second conductive segments in a second conductive layer running in a second direction and a plurality of interlayer vias between the first conductive layer and the second conductive layer. The second direction is substantially vertical to the first direction. The plurality of second conductive segments overlap with the first conductive segment. The plurality of interlayer vias are formed at where the plurality of second conductive segments overlap with the first conductive segment. Each of the plurality of second conductive segments has a width such that the first conductive segment has a first unit spacing with a first adjacent conductive line or one of the plurality of second conductive segments has a second unit spacing with a second adjacent conductive line.

公开(公告)号：US10074641B2

公开(公告)日：2018-09-11

申请号：US15791320

申请日：2017-10-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC分类号： H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L21/768 ,  H01L23/50 ,  H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/822 ,  H01L23/532 ,  H01L21/324

CPC分类号： H01L27/0207 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

公开(公告)号：US08937358B2

公开(公告)日：2015-01-20

申请号：US13874055

申请日：2013-04-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC分类号： H01L21/70 ,  H01L27/07

CPC分类号： H01L29/66545 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/11807

摘要： An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

公开(公告)号：US20140239410A1

公开(公告)日：2014-08-28

申请号：US13829484

申请日：2013-03-14

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC分类号： H01L27/02

CPC分类号： H01L27/0207 ,  H01L27/11807

摘要： A die includes a plurality of rows of standard cells. Each of all standard cells in the plurality of rows of standard cells includes a transistor and a source edge, wherein a source region of the transistor is adjacent to the source edge. No drain region of any transistor in the each of all standard cells is adjacent to the source region.

摘要翻译： 芯片包括多行标准单元。 多行标准单元中的每个标准单元包括晶体管和源极边缘，其中晶体管的源极区域与源极边缘相邻。 所有标准单元中的每一个中的任何晶体管的漏极区域都不与源极区域相邻。

公开(公告)号：US09984192B2

公开(公告)日：2018-05-29

申请号：US15043858

申请日：2016-02-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5081

摘要： An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.

公开(公告)号：US09509301B2

公开(公告)日：2016-11-29

申请号：US13931514

申请日：2013-06-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jerry Chang-Jui Kao ,  Chien-Ju Chao ,  Chou-Kun Lin ,  Chin-Shen Lin ,  King-Ho Tam ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC分类号： H02M3/156 ,  H03K17/296 ,  H03K17/284

CPC分类号： H03K17/296 ,  H03K17/284 ,  Y10T307/406

摘要： A circuit is disclosed that includes a plurality of voltage control circuits. Each voltage control circuit of the voltage control circuits includes a driver circuit and a switch circuit. The driver circuit is configured to receive a control signal having a series of pulses. The switch circuit is configured to generate a driving voltage when being turned on. The driver circuit alternately turns on and off the switch circuit in accordance with the series of pulses.

摘要翻译： 公开了一种包括多个电压控制电路的电路。 电压控制电路的每个电压控制电路包括驱动电路和开关电路。 驱动器电路被配置为接收具有一系列脉冲的控制信号。 开关电路被配置为在导通时产生驱动电压。 驱动器电路根据该脉冲串交替地接通和断开开关电路。

公开(公告)号：US20150118812A1

公开(公告)日：2015-04-30

申请号：US14543991

申请日：2014-11-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC分类号： H01L29/66 ,  H01L21/8234

CPC分类号： H01L29/66545 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/11807

摘要： An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

摘要翻译： 集成电路包括第一和第二标准单元。 第一标准单元包括第一栅极电极和第一栅极电极下面的第一沟道区域。 第一通道区域具有第一通道掺杂浓度。 第二标准单元包括第二栅极电极和第二栅极电极下面的第二沟道区域。 第二沟道区具有第二沟道掺杂浓度。 虚拟栅极分别包括第一和第二标准单元中的前半部分和第二半部分。 第一半和第二半分别在第一标准单元和第二标准单元的边缘处并且彼此抵接。 虚拟通道由虚拟门重叠。 虚拟通道具有基本上等于第一通道掺杂浓度和第二通道掺杂浓度之和的第三通道掺杂浓度。

公开(公告)号：US20160197068A1

公开(公告)日：2016-07-07

申请号：US15070904

申请日：2016-03-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC分类号： H01L27/02 ,  H01L23/50 ,  H01L27/06 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238

CPC分类号： H01L27/0207 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

公开(公告)号：US09262573B2

公开(公告)日：2016-02-16

申请号：US13791406

申请日：2013-03-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5081

摘要： An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.

摘要翻译： 实施例小区移位方案包括将第一晶体管单元抵靠第二晶体管单元并将位置和布线边界移离设置在第一晶体管单元和第二晶体管单元之间的多晶硅。 在一个实施例中，小区移位方案包括移动位置和路由边界以防止布局与示意图（LVS）网表和后仿真网表之间的不匹配。

公开(公告)号：US09047433B2

公开(公告)日：2015-06-02

申请号：US13874027

申请日：2013-04-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.

摘要翻译： 芯片包括至少一个标准单元，其包括与第一边界相对的第一边界和第二边界。 第一边界和第二边界平行于第一方向。 所述至少一个标准单元还包括第一多个FinFET，其包括平行于所述第一方向的第一半导体鳍片。 芯片还包括至少一个存储器宏，其具有与第三边界相反的第三边界和第四边界。 第三边界和第四边界与第一方向平行。 至少一个存储器宏包括第二多个FinFET，其包括平行于第一方向的第二半导体鳍片。 所述至少一个标准单元和所述至少一个存储器宏中的所有半导体鳍具有等于所述第一和第二半导体鳍的最小间距的整数倍的间距。