公开(公告)号：US09984192B2

公开(公告)日：2018-05-29

申请号：US15043858

申请日：2016-02-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.

公开(公告)号：US20150118812A1

公开(公告)日：2015-04-30

申请号：US14543991

申请日：2014-11-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/11807

Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

Abstract translation: 集成电路包括第一和第二标准单元。 第一标准单元包括第一栅极电极和第一栅极电极下面的第一沟道区域。 第一通道区域具有第一通道掺杂浓度。 第二标准单元包括第二栅极电极和第二栅极电极下面的第二沟道区域。 第二沟道区具有第二沟道掺杂浓度。 虚拟栅极分别包括第一和第二标准单元中的前半部分和第二半部分。 第一半和第二半分别在第一标准单元和第二标准单元的边缘处并且彼此抵接。 虚拟通道由虚拟门重叠。 虚拟通道具有基本上等于第一通道掺杂浓度和第二通道掺杂浓度之和的第三通道掺杂浓度。

公开(公告)号：US20180047716A1

公开(公告)日：2018-02-15

申请号：US15791320

申请日：2017-10-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L27/02 ,  H01L23/528 ,  H01L21/768 ,  H01L23/50 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L27/0207 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

公开(公告)号：US09799639B2

公开(公告)日：2017-10-24

申请号：US15070904

申请日：2016-03-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L27/02 ,  H01L27/06 ,  H01L23/528 ,  H01L23/50 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/324 ,  H01L23/532

CPC classification number: H01L27/0207 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

公开(公告)号：US20150348962A1

公开(公告)日：2015-12-03

申请号：US14470716

申请日：2014-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L27/06 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/324 ,  H01L27/02 ,  H01L23/50

CPC classification number: H01L27/0207 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

Abstract translation: 在本公开中描述了在多个有源器件层上形成功率门控单元和虚拟功率电路的机构的实施例。 电源门控单元和虚拟电源电路形成在单独的有源器件层上，以允许与电源连接的互连结构形成在与用于连接电源门控单元和虚拟电源电路的互连结构的单独级别上。 这种分离防止这两种类型的互连结构竞争相同的空间。 两种类型的互连结构的路由变得更加容易。 结果，互连结构的金属长度减小并且金属宽度增加。 减少金属长度和增加的金属宽度降低电阻，提高电阻 - 电容（RC）延迟和电气性能，并提高互连可靠性，如减少电迁移。

公开(公告)号：US09171926B2

公开(公告)日：2015-10-27

申请号：US14543991

申请日：2014-11-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC: H01L21/8236 ,  H01L29/66 ,  H01L27/02 ,  H01L27/118 ,  H01L27/07 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/11807

Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

Abstract translation: 集成电路包括第一和第二标准单元。 第一标准单元包括第一栅极电极和第一栅极电极下面的第一沟道区域。 第一通道区域具有第一通道掺杂浓度。 第二标准单元包括第二栅极电极和第二栅极电极下面的第二沟道区域。 第二沟道区具有第二沟道掺杂浓度。 虚拟栅极分别包括第一和第二标准单元中的前半部分和第二半部分。 第一半和第二半分别在第一标准单元和第二标准单元的边缘处并且彼此抵接。 虚拟通道由虚拟门重叠。 虚拟通道具有基本上等于第一通道掺杂浓度和第二通道掺杂浓度之和的第三通道掺杂浓度。

公开(公告)号：US11239154B2

公开(公告)日：2022-02-01

申请号：US14600619

申请日：2015-01-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chien-Ju Chao ,  Fang-Yu Fan ,  Yi-Chuin Tsai ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L23/522 ,  H01L23/528 ,  G06F30/394

Abstract: In some embodiments, a fishbone structure in a power network includes a first conductive segment in a first conductive layer running in a first direction, a plurality of second conductive segments in a second conductive layer running in a second direction and a plurality of interlayer vias between the first conductive layer and the second conductive layer. The second direction is substantially vertical to the first direction. The plurality of second conductive segments overlap with the first conductive segment. The plurality of interlayer vias are formed at where the plurality of second conductive segments overlap with the first conductive segment. Each of the plurality of second conductive segments has a width such that the first conductive segment has a first unit spacing with a first adjacent conductive line or one of the plurality of second conductive segments has a second unit spacing with a second adjacent conductive line.

公开(公告)号：US10074641B2

公开(公告)日：2018-09-11

申请号：US15791320

申请日：2017-10-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L21/768 ,  H01L23/50 ,  H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/822 ,  H01L23/532 ,  H01L21/324

CPC classification number: H01L27/0207 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

公开(公告)号：US08937358B2

公开(公告)日：2015-01-20

申请号：US13874055

申请日：2013-04-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC: H01L21/70 ,  H01L27/07

CPC classification number: H01L29/66545 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/0705 ,  H01L27/11807

Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

公开(公告)号：US20140239410A1

公开(公告)日：2014-08-28

申请号：US13829484

申请日：2013-03-14

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Kuo-Nan Yang ,  Chou-Kun Lin ,  Jerry Chang-Jui Kao ,  Yi-Chuin Tsai ,  Chien-Ju Chao ,  Chung-Hsing Wang

IPC: H01L27/02

CPC classification number: H01L27/0207 ,  H01L27/11807

Abstract: A die includes a plurality of rows of standard cells. Each of all standard cells in the plurality of rows of standard cells includes a transistor and a source edge, wherein a source region of the transistor is adjacent to the source edge. No drain region of any transistor in the each of all standard cells is adjacent to the source region.

Abstract translation: 芯片包括多行标准单元。 多行标准单元中的每个标准单元包括晶体管和源极边缘，其中晶体管的源极区域与源极边缘相邻。 所有标准单元中的每一个中的任何晶体管的漏极区域都不与源极区域相邻。