Invention Grant
- Patent Title: Power gating for three dimensional integrated circuits (3DIC)
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Application No.: US15070904Application Date: 2016-03-15
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Publication No.: US09799639B2Publication Date: 2017-10-24
- Inventor: Chien-Ju Chao , Chou-Kun Lin , Yi-Chuin Tsai , Yen-Hung Lin , Po-Hsiang Huang , Kuo-Nan Yang , Chung-Hsing Wang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L27/06 ; H01L23/528 ; H01L23/50 ; H01L21/768 ; H01L21/8234 ; H01L21/822 ; H01L21/8238 ; H01L27/092 ; H01L21/324 ; H01L23/532

Abstract:
Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.
Public/Granted literature
- US20160197068A1 Power Gating for Three Dimensional Integrated Circuits (3DIC) Public/Granted day:2016-07-07
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