公开(公告)号：US12176288B2

公开(公告)日：2024-12-24

申请号：US17585715

申请日：2022-01-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wan-Yu Lo ,  Chin-Shen Lin ,  Chi-Yu Lu ,  Kuo-Nan Yang ,  Chih-Liang Chen ,  Chung-Hsing Wang

IPC: H01L23/528 ,  H01L23/50 ,  H01L27/088 ,  H01L27/118

Abstract: Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate, a power switch, a first power mesh and a second power mesh. The power switch is formed over the front surface of the semiconductor substrate. The first power mesh is formed over the power switch and is directly connected to the first terminal of the power switch. The second power mesh is formed over the back surface of the semiconductor substrate and is directly connected to the second terminal of the power switch.

公开(公告)号：US12159899B2

公开(公告)日：2024-12-03

申请号：US18335162

申请日：2023-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Kuo-Nan Yang

IPC: H01L29/06 ,  H01L27/092

Abstract: A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.

公开(公告)号：US12033998B2

公开(公告)日：2024-07-09

申请号：US18363230

申请日：2023-08-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuang-Ching Chang ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Kuo-Nan Yang

IPC: H01L27/02 ,  G06F1/3287

CPC classification number: H01L27/0207 ,  G06F1/3287

Abstract: An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The first power rail includes a first portion, a second portion and a third portion, the third portion being between the first portion and the second portion. The second power rail is configured to supply the second voltage to the gated circuit, and is between the first portion and the second portion. The third power rail includes a first set of conductors. Each of the first set of conductors being configured to supply a third voltage to the header circuit.

公开(公告)号：US20240096803A1

公开(公告)日：2024-03-21

申请号：US18517706

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Hsiung Chen ,  Jerry Chang Jui Kao ,  Kuo-Nan Yang ,  Jack Liu

IPC: H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5286 ,  G06F30/392 ,  G06F30/394 ,  H01L21/76877 ,  H01L23/5226

Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.

公开(公告)号：US11855632B2

公开(公告)日：2023-12-26

申请号：US17115571

申请日：2020-12-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shao-Huan Wang ,  Chun-Chen Chen ,  Sheng-Hsiung Chen ,  Kuo-Nan Yang

IPC: H03K19/17704 ,  H01L23/528 ,  H03K19/17736 ,  H01L27/02 ,  G06F30/392

CPC classification number: H03K19/17704 ,  G06F30/392 ,  H01L23/528 ,  H01L27/0207 ,  H03K19/17736

Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.

公开(公告)号：US11854978B2

公开(公告)日：2023-12-26

申请号：US17332072

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Hsiung Chen ,  Jerry Chang Jui Kao ,  Kuo-Nan Yang ,  Jack Liu

IPC: H01L23/528 ,  H01L23/522 ,  G06F30/394 ,  G06F30/392 ,  H01L21/768

CPC classification number: H01L23/5286 ,  G06F30/392 ,  G06F30/394 ,  H01L21/76877 ,  H01L23/5226

Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.

公开(公告)号：US11347922B2

公开(公告)日：2022-05-31

申请号：US17195094

申请日：2021-03-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hiranmay Biswas ,  Chung-Hsing Wang ,  Chin-Shen Lin ,  Kuo-Nan Yang

IPC: G06F30/392 ,  G06F30/3947 ,  G06F30/3953 ,  G06F30/394 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L23/00

Abstract: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first conductive layer including segments which are conductive, including forming first segments designated for a first reference voltage and second segments designated for a second reference voltage, and interspersing the first and second segments; relative to a first direction; and forming a second conductive layer over the first conductive layer, the second conductive layer including segments that are conductive, including forming third segments designated for the first reference voltage and fourth segments designated for the second reference voltage, interspersing the third and fourth segments relative to a second direction, the second direction being perpendicular to the first direction, and arranging the segments in the second conductive layer substantially asymmetrically including, relative to the first direction, locating each fourth segment substantially asymmetrically between corresponding adjacent ones of the third segments.

公开(公告)号：US11211327B2

公开(公告)日：2021-12-28

申请号：US16731719

申请日：2019-12-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiranmay Biswas ,  Chin-Shen Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F30/394 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118 ,  H01L21/768 ,  H01L23/522

Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

公开(公告)号：US09953122B2

公开(公告)日：2018-04-24

申请号：US15210052

申请日：2016-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Yu-Jen Chang ,  Kuo-Nan Yang ,  Jui-Jung Hsu ,  Chih-Hung Wu ,  Chung-Hsing Wang

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/82 ,  G06F2217/84

Abstract: An integrated circuit (IC) design method is disclosed. The method includes: using a computer to perform synthesis upon a register transfer level (RTL) IC design to generate a gate level netlist; performing place and route (P&R) upon the gate level netlist to generate a layout; determining a sink current distribution information of the layout; and generating a voltage (IR) drop/electro-migration (EM) analysis result of the layout according to the sink current distribution information; wherein the layout includes a cell having a cell height that is N times higher than a single cell height, where N is an integer and greater than 1, and the cell corresponds to N power/ground (P/G) rail sets; wherein the sink current distribution information includes a proportion of a sink current flowing through each of the N power/ground (P/G) rail sets with respect to the cell when operated. Associated non-transitory computer-readable medium is also disclosed.

公开(公告)号：US20160197068A1

公开(公告)日：2016-07-07

申请号：US15070904

申请日：2016-03-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Ju Chao ,  Chou-Kun Lin ,  Yi-Chuin Tsai ,  Yen-Hung Lin ,  Po-Hsiang Huang ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L27/02 ,  H01L23/50 ,  H01L27/06 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238

CPC classification number: H01L27/0207 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.