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    Method, system, and storage medium of resource planning for designing semiconductor device
    3.
    发明授权
    Method, system, and storage medium of resource planning for designing semiconductor device 有权

    公开(公告)号：US11574106B2

    公开(公告)日：2023-02-07

    申请号：US17193396

    申请日：2021-03-05

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Yuan-Te Hou

    IPC: G06F9/455 ,  G06F30/392 ,  G06F30/398

    Abstract: A method includes: accessing a design data of an integrated circuit (IC), wherein the design data includes a transistor layer and a plurality of metal layers over the transistor layer; assigning a bin size for each of the metal layers based on layout properties of the respective metal layers, wherein a bin size of a higher larger of the metal layers has a greater bin size than that of a lower layer of the metal layers; performing resource planning on the transistor layer and each of the metal layers according to the assigned bin sizes of the respective metal layers; and updating the design data according to the resource planning. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.

    Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement
    6.
    发明授权
    Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement 有权

    公开(公告)号：US11347922B2

    公开(公告)日：2022-05-31

    申请号：US17195094

    申请日：2021-03-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Hiranmay Biswas ,  Chung-Hsing Wang ,  Chin-Shen Lin ,  Kuo-Nan Yang

    IPC: G06F30/392 ,  G06F30/3947 ,  G06F30/3953 ,  G06F30/394 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L23/00

    Abstract: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first conductive layer including segments which are conductive, including forming first segments designated for a first reference voltage and second segments designated for a second reference voltage, and interspersing the first and second segments; relative to a first direction; and forming a second conductive layer over the first conductive layer, the second conductive layer including segments that are conductive, including forming third segments designated for the first reference voltage and fourth segments designated for the second reference voltage, interspersing the third and fourth segments relative to a second direction, the second direction being perpendicular to the first direction, and arranging the segments in the second conductive layer substantially asymmetrically including, relative to the first direction, locating each fourth segment substantially asymmetrically between corresponding adjacent ones of the third segments.

    Via sizing for IR drop reduction
    7.
    发明授权
    Via sizing for IR drop reduction 有权

    公开(公告)号：US11211327B2

    公开(公告)日：2021-12-28

    申请号：US16731719

    申请日：2019-12-31

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Hiranmay Biswas ,  Chin-Shen Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

    IPC: G06F30/394 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118 ,  H01L21/768 ,  H01L23/522

    Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

    Multiple patterning method and system for implementing the method
    8.
    发明授权
    Multiple patterning method and system for implementing the method 有权

    公开(公告)号：US10990741B2

    公开(公告)日：2021-04-27

    申请号：US16676822

    申请日：2019-11-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Yuan-Te Hou

    IPC: G06F30/30 ,  G06F30/392 ,  G06F30/394

    Abstract: A method includes assigning a first color group to a first routing track of the layout. The method further includes assigning a second color group to a second routing track of the layout. The method includes assigning the first color group to a third routing track of the layout, wherein the second routing track is between the first routing track and the third routing track. The method further includes assigning a first color from the first color group to a first conductive element along the first routing track. The method further includes assigning a second color from the first color group to a second conductive element along the first routing track. The method further includes assigning a third color from the second color group to a third conductive element on the second routing track, wherein the third color is different from each of the first color and the second color.

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