公开(公告)号：US20220173222A1

公开(公告)日：2022-06-02

申请号：US17676380

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Hsin-Yi Lee ,  Hsuan-Yu Tung ,  Chin-You Hsu ,  Cheng-Lung Hung

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.

公开(公告)号：US12068388B2

公开(公告)日：2024-08-20

申请号：US17676380

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Hsuan-Yu Tung ,  Chin-You Hsu ,  Cheng-Lung Hung

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28247 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.

公开(公告)号：US11961732B2

公开(公告)日：2024-04-16

申请号：US17814716

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Chung-Chiang Wu ,  Shih-Hang Chiu ,  Hsuan-Yu Tung ,  Da-Yuan Lee

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/02175 ,  H01L21/76841 ,  H01L21/76871 ,  H01L27/0886 ,  H01L29/66871

Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

公开(公告)号：US20240363627A1

公开(公告)日：2024-10-31

申请号：US18767022

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Chang Chiu ,  Chia-Ching Lee ,  Chien-Hao Chen ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chi On Chui ,  Hsuan-Yu Tung ,  Chung-Chiang Wu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/6681 ,  H01L29/785

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

公开(公告)号：US20240222108A1

公开(公告)日：2024-07-04

申请号：US18608560

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Chung-Chiang Wu ,  Shih-Hang Chiu ,  Hsuan-Yu Tung ,  Da-Yuan Lee

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/02175 ,  H01L21/76841 ,  H01L21/76871 ,  H01L27/0886 ,  H01L29/66871

Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

公开(公告)号：US20220336619A1

公开(公告)日：2022-10-20

申请号：US17854749

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hung-Chin Chung ,  Chung-Chiang Wu ,  Hsuan-Yu Tung ,  Kuan-Chang Chiu ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/8234

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

公开(公告)号：US20210273070A1

公开(公告)日：2021-09-02

申请号：US16889217

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hung-Chin Chung ,  Chung-Chiang Wu ,  Hsuan-Yu Tung ,  Kuan-Chang Chiu ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

公开(公告)号：US20240387679A1

公开(公告)日：2024-11-21

申请号：US18787716

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hung-Chin Chung ,  Chung-Chiang Wu ,  Hsuan-Yu Tung ,  Kuan-Chang Chiu ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

公开(公告)号：US20240363719A1

公开(公告)日：2024-10-31

申请号：US18770040

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Hsuan-Yu Tung ,  Chin-You Hsu ,  Cheng-Lung Hung

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28247 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.

公开(公告)号：US12087767B2

公开(公告)日：2024-09-10

申请号：US18068647

申请日：2022-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Chang Chiu ,  Chia-Ching Lee ,  Chien-Hao Chen ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chi On Chui ,  Hsuan-Yu Tung ,  Chung-Chiang Wu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/6681 ,  H01L29/785

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.