公开(公告)号：US20190096681A1

公开(公告)日：2019-03-28

申请号：US16203832

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu ,  Hsin-Yun Hsu ,  Pin-Hsuan Yeh

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/285

Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

公开(公告)号：US20220173222A1

公开(公告)日：2022-06-02

申请号：US17676380

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Hsin-Yi Lee ,  Hsuan-Yu Tung ,  Chin-You Hsu ,  Cheng-Lung Hung

IPC: H01L29/49 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.

公开(公告)号：US10707318B2

公开(公告)日：2020-07-07

申请号：US15877391

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Fen Chien ,  Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/28 ,  H01L29/165

Abstract: Provided is a semiconductor device including a fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer is disposed over the second layer. The second layer includes a base material and a dopant doped in the base material. The dopant comprises Al, Ta, W, or a combination thereof. The first layer and the second layer comprise different materials. A method of manufacturing the semiconductor device is also provided.

公开(公告)号：US12068388B2

公开(公告)日：2024-08-20

申请号：US17676380

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Hsuan-Yu Tung ,  Chin-You Hsu ,  Cheng-Lung Hung

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28247 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.

公开(公告)号：US20230317457A1

公开(公告)日：2023-10-05

申请号：US18330885

申请日：2023-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu ,  Hsin-Yun Hsu ,  Pin-Hsuan Yeh

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/285 ,  H01L29/40 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L21/28185 ,  H01L29/513 ,  H01L21/28556 ,  H01L29/401 ,  H01L29/4966 ,  H01L21/32134 ,  H01L21/02321 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28568 ,  H01L29/785

Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

公开(公告)号：US11710638B2

公开(公告)日：2023-07-25

申请号：US17334255

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu ,  Hsin-Yun Hsu ,  Pin-Hsuan Yeh

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/285 ,  H01L29/40 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28185 ,  H01L21/02321 ,  H01L21/28556 ,  H01L21/32134 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/28568 ,  H01L29/66795 ,  H01L29/785

Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

公开(公告)号：US20240363719A1

公开(公告)日：2024-10-31

申请号：US18770040

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Hsuan-Yu Tung ,  Chin-You Hsu ,  Cheng-Lung Hung

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28247 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.

公开(公告)号：US20210287905A1

公开(公告)日：2021-09-16

申请号：US17334255

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu ,  Hsin-Yun Hsu ,  Pin-Hsuan Yeh

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/285 ,  H01L29/40 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/02

Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

公开(公告)号：US11088257B2

公开(公告)日：2021-08-10

申请号：US16884053

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Fen Chien ,  Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/165

Abstract: Provided is a semiconductor device including a first n-type fin field effect transistor (FinFET) and a second n-type FinFET. The first FinFET includes a first work function layer. The first work function layer includes a first portion of a first layer. The second n-type FinFET includes a second work function layer. The second work function layer includes a second portion of the first layer and a first portion of a second layer underlying the second portion of the first layer. A thickness of the first work function layer is less than a thickness of the second work function layer. A method of manufacturing the semiconductor device is also provided.

公开(公告)号：US11024505B2

公开(公告)日：2021-06-01

申请号：US16203832

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Kuan Wei ,  Hsien-Ming Lee ,  Chin-You Hsu ,  Hsin-Yun Hsu ,  Pin-Hsuan Yeh

IPC: H01L21/28 ,  H01L29/51 ,  H01L21/285 ,  H01L29/40 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.