公开(公告)号：US20250142919A1

公开(公告)日：2025-05-01

申请号：US19009809

申请日：2025-01-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY ,  NATIONAL TAIWAN NORMAL UNIVERSITY

Inventor： Tung-Ying LEE ,  Tse-An CHEN ,  Tzu-Chung WANG ,  Miin-Jang CHEN ,  Yu-Tung YIN ,  Meng-Chien YANG

IPC: H10D64/01 ,  H01L21/02 ,  H01L21/28 ,  H10D30/01 ,  H10D30/62 ,  H10D30/67 ,  H10D62/10

Abstract: A semiconductor device includes a channel structure, source region, a drain region, metal gate structure, and a self-assembled layer. The source region and the drain region are on opposite sides of the channel structure. A bottom surface of the source region is lower than a bottom surface of the channel structure, and a top surface of the source region is higher than a top surface of the channel structure. The metal gate structure covers the channel structure and between the source region and the drain region. The self-assembled layer is between the source region and the metal gate structure. The self-assembled layer is in contact with the bottom surface of the channel structure but spaced apart from the top surface of the channel structure.

公开(公告)号：US20220310919A1

公开(公告)日：2022-09-29

申请号：US17839322

申请日：2022-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chao LIN ,  Yuan-Tien TU ,  Shao-Ming YU ,  Tung-Ying LEE

IPC: H01L45/00

Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating.

公开(公告)号：US20210020763A1

公开(公告)日：2021-01-21

申请号：US17065235

申请日：2020-10-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng YUN ,  Shao-Ming YU ,  Tung-Ying LEE ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A device includes a semiconductor fin, a first epitaxy structure and a gate stack. The semiconductor fin protrudes from a substrate. The first epitaxy feature laterally surrounds a first portion of the semiconductor fin. The gate stack laterally surrounds a second portion of the semiconductor fin above the first portion of the semiconductor fin, wherein the second portion of the semiconductor fin has a lower surface roughness than the first epitaxy feature.

公开(公告)号：US20200321336A1

公开(公告)日：2020-10-08

申请号：US16910297

申请日：2020-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Winnie Victoria Wei-Ning CHEN ,  Meng-Hsuan HSIAO ,  Tung-Ying LEE ,  Pang-Yen TSAI ,  Yasutoshi OKUNO

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H01L21/306 ,  H01L29/16 ,  H01L21/02 ,  H01L29/10 ,  H01L21/8238

Abstract: A method for forming a semiconductor device is provided. The method includes removing a first portion of a substrate to form a recess in the substrate. The method includes forming an epitaxy layer in the recess. The epitaxy layer and the substrate are made of different semiconductor materials. The method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate and the epitaxy layer. The method includes removing a second portion of the stacked structure and a third portion of the epitaxy layer to form trenches passing through the stacked structure and extending into the epitaxy layer, The stacked structure is divided into a first fin element and a second fin element by the trenches, and the first fin element and the second fin element are over the substrate and the epitaxy layer respectively.

公开(公告)号：US20200152870A1

公开(公告)日：2020-05-14

申请号：US16509105

申请日：2019-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chao LIN ,  Yuan-Tien TU ,  Shao-Ming YU ,  Tung-Ying LEE

IPC: H01L45/00

Abstract: A method of forming a phase change random access memory (PCRAM) device includes forming a phase change element over a bottom electrode and a top electrode over the phase change element, forming a protection layer around the phase change element, and forming a nitrogen-containing sidewall spacer layer around the protection layer after forming the protection layer.

公开(公告)号：US20230238451A1

公开(公告)日：2023-07-27

申请号：US18194886

申请日：2023-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng YUN ,  Shao-Ming YU ,  Tung-Ying LEE ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66666 ,  H01L29/66787 ,  H01L29/7827 ,  H01L29/0847 ,  H01L29/78642

Abstract: A device includes a plurality of semiconductor fins extending from a substrate. A plurality of first source/drain regions are epitaxially grown from first regions of the semiconductor fins. Adjacent two of the plurality of first source/drain regions grown from adjacent two of the plurality of semiconductor fins are spaced apart by an isolation dielectric. A gate structure laterally surrounds second regions of the plurality of semiconductor fins above the first regions of the plurality of semiconductor fins. A plurality of second source/drain regions are over third regions of the plurality of semiconductor fins above the second regions of the plurality of semiconductor fins.

公开(公告)号：US20220238523A1

公开(公告)日：2022-07-28

申请号：US17718182

申请日：2022-04-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi PENG ,  Chun-Chieh LU ,  Meng-Hsuan HSIAO ,  Ling-Yen YEH ,  Carlos H. DIAZ ,  Tung-Ying LEE

IPC: H01L27/092 ,  H01L23/532 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L21/768 ,  H01L21/02 ,  H01L23/538 ,  H01L29/423 ,  H01L29/778 ,  H01L29/45 ,  H01L27/12 ,  H01L29/06 ,  G06F16/955 ,  G06F3/0481 ,  G06F13/00 ,  H04L9/40 ,  H04L67/303 ,  H04L67/306

Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

公开(公告)号：US20220149177A1

公开(公告)日：2022-05-12

申请号：US17586083

申请日：2022-01-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY ,  NATIONAL TAIWAN NORMAL UNIVERSITY

Inventor： Tung-Ying LEE ,  Tse-An CHEN ,  Tzu-Chung WANG ,  Miin-Jang CHEN ,  Yu-Tung YIN ,  Meng-Chien YANG

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02

Abstract: A semiconductor device includes source and a drain above a substrate and spaced apart along a first direction, and a semiconductor channel extending between the source and the drain. The semiconductor device further includes gate spacers, an interfacial layer, and a metal gate structure. The gate spacers are disposed on the semiconductor channel and spaced apart by a spacer-to-spacer distance along the first direction. The interfacial layer is on the semiconductor channel. The interfacial layer extends a length along the first direction, and the length is less than a minimum of the spacer-to-spacer distance along the first direction. The metal gate structure is over the interfacial layer.

公开(公告)号：US20210183855A1

公开(公告)日：2021-06-17

申请号：US16895795

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jin-Aun NG ,  Yu-Chao LIN ,  Tung-Ying LEE

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first gate-all-around FET over a substrate, and the first gate-all-around FET includes first nanostructures and a first gate stack surrounding the first nanostructures. The semiconductor structure also includes a first FinFET adjacent to the first gate-all-around FET, and the first FinFET includes a first fin structure and a second gate stack over the first fin structure. The semiconductor structure also includes a gate-cut feature interposing the first gate stack of the first gate-all-around FET and the second gate stack of the first FinFET

公开(公告)号：US20180337034A1

公开(公告)日：2018-11-22

申请号：US15598439

申请日：2017-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Ying LEE ,  Shao-Ming YU

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/34

CPC classification number: H01L21/0243 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/16 ,  H01L29/34

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a first semiconductor layer, a second dielectric layer and a second semiconductor layer. The first dielectric layer is disposed on the substrate and includes at least one first trench formed in the first dielectric layer. The first semiconductor layer is disposed on the first dielectric layer and within the at least one first trench. The second dielectric layer is disposed on the first semiconductor layer and includes at least one second trench formed in the second dielectric layer, wherein in a planar view, the at least one first trench and the at least one second trench are not overlapped with each other. The second semiconductor layer is disposed on the second dielectric layer and within the at least one second trench.