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公开(公告)号：US11257898B2
公开(公告)日：2022-02-22
申请号：US16908237
申请日：2020-06-22
IPC分类号： H01L49/02 , H01L23/522 , H01F27/28 , H03L7/085 , H03L7/099 , B01D1/00 , B01D1/12 , C02F1/04 , C02F11/12 , C02F11/18 , C02F101/30 , C02F103/14 , C02F103/16 , C02F103/28 , C02F103/32 , C02F103/34 , C02F103/36
摘要： In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.
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公开(公告)号：US20230387180A1
公开(公告)日：2023-11-30
申请号：US18232332
申请日：2023-08-09
IPC分类号： H03L7/099 , H03L7/085 , C02F11/18 , B01D1/00 , H01F27/28 , C02F1/04 , C02F11/12 , H01L23/522 , B01D1/12 , C02F103/32 , C02F103/28 , C02F101/30 , C02F103/16 , C02F103/34 , C02F103/14 , C02F103/36
CPC分类号： H01L28/10 , H03L7/085 , H03L7/099 , C02F11/18 , B01D1/0017 , H01F27/2885 , C02F1/048 , C02F11/12 , H01L23/5227 , B01D1/12 , H03L2207/50 , C02F2103/32 , C02F2103/28 , C02F2101/301 , C02F2103/16 , C02F2103/343 , C02F2101/306 , C02F2103/14 , C02F2103/365
摘要： In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.
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公开(公告)号：US11139778B1
公开(公告)日：2021-10-05
申请号：US16836405
申请日：2020-03-31
IPC分类号： H03B5/12
摘要： Apparatus, circuits and methods for clock generation are disclosed herein. In some embodiments, an apparatus is disclosed. The apparatus includes: a first transistor pair electrically coupled to a pair of output nodes; a second transistor pair electrically coupled to the pair of output nodes; and an inductive unit electrically coupled between the output nodes and electrically coupled between gates of the first transistor pair. The inductive unit comprises: a first inductive element electrically coupled to one gate of the first transistor pair; and a second inductive element electrically coupled to one of the output nodes. The first inductive element and the second inductive element are configured to be magnetically coupled to each other.
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公开(公告)号：US20180351558A1
公开(公告)日：2018-12-06
申请号：US15965110
申请日：2018-04-27
发明人： Feng Wei KUO , Chewn-pu Jou , Huan-Neng Chen , Lan-Chou Cho , Robert Bogdan Staszewski , Seyednaser Pourmousavian
CPC分类号： H03L1/00 , G04F10/005 , H03L7/093 , H03L7/0991
摘要： An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.
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公开(公告)号：US11770106B2
公开(公告)日：2023-09-26
申请号：US17230841
申请日：2021-04-14
发明人： Feng-Wei Kuo , Kai Xu , Robert Bogdan Staszewski
CPC分类号： H03F1/565 , H03F3/20 , H03F3/45 , H03F2200/451
摘要： Systems and methods for suppressing and mitigating harmonic distortion in a circuit are disclosed. In one example, a disclosed circuit includes a radio frequency (RF) oscillator and a power amplifier. The RF oscillator is configured to generate an RF signal. The power amplifier is configured to generate an amplified RF signal based on the RF signal. The power amplifier includes a transformer including a primary winding and a secondary winding, and a feedback capacitor electrically coupled to the primary winding and the secondary winding.
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公开(公告)号：US10985709B2
公开(公告)日：2021-04-20
申请号：US16291709
申请日：2019-03-04
发明人： Feng-Wei Kuo , Kai Xu , Robert Bogdan Staszewski
摘要： Systems and methods for suppressing and mitigating harmonic distortion in a circuit are disclosed. In one example, a disclosed circuit includes a radio frequency (RF) oscillator and a power amplifier. The RF oscillator is configured to generate an RF signal. The power amplifier is configured to generate an amplified RF signal based on the RF signal. The power amplifier includes a transformer including a primary winding and a secondary winding, and a feedback capacitor electrically coupled to the primary winding and the secondary winding.
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公开(公告)号：US10862486B2
公开(公告)日：2020-12-08
申请号：US16429774
申请日：2019-06-03
发明人： Feng Wei Kuo , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho , Robert Bogdan Staszewski , Seyednaser Pourmousavian
摘要： An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.
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公开(公告)号：US10270486B2
公开(公告)日：2019-04-23
申请号：US15900594
申请日：2018-02-20
发明人： Feng-Wei Kuo , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho , Robert Bogdan Staszewski , Sandro Binsfeld Ferreira
摘要： An ultra-low-power receiver includes a low-noise amplifier configured to receive an input analog signal and generate an amplified signal and a mixer electrically coupled to the low-noise amplifier. The mixer is configured to convert said amplified signal into an intermediate frequency signal. A progressively reduced intermediate frequency filter is configured to process the intermediate frequency signal from the mixer in discrete time.
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公开(公告)号：US11177810B2
公开(公告)日：2021-11-16
申请号：US17112450
申请日：2020-12-04
发明人： Feng Wei Kuo , Chewn-Pu Jou , Huan-Neng Chen , Lan-Chou Cho , Robert Bogdan Staszewski , Seyednaser Pourmousavian
摘要： An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations. The digital circuitry regulates the digital input supply voltage to stabilize the resolution of the TDC across the PVT variations. This stabilization of the resolution of the TDC can cause the ADPLL to maintain a fixed in-band phase noise across the PVT variations.
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公开(公告)号：US10692963B2
公开(公告)日：2020-06-23
申请号：US15965476
申请日：2018-04-27
IPC分类号： H01F27/28 , H01L23/522 , H01L49/02 , H03L7/085 , H03L7/099
摘要： In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.
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