SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20210210616A1

    公开(公告)日:2021-07-08

    申请号:US17157180

    申请日:2021-01-25

    Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号:US20150200299A1

    公开(公告)日:2015-07-16

    申请号:US14224961

    申请日:2014-03-25

    Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.

    Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括衬底; 在衬底中具有第一掺杂剂的源/漏区; 阻挡层,其具有形成在衬底中的源极/漏极区周围的第二掺杂物。 当半导体器件按比例缩小时,源极/漏极区域中的掺杂分布可能影响阈值电压均匀性,所提供的半导体器件可以通过阻挡层来改善阈值电压均匀性以控制掺杂分布。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20250072082A1

    公开(公告)日:2025-02-27

    申请号:US18938087

    申请日:2024-11-05

    Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

    MECHANISM FOR FORMING SEMICONDUCTOR DEVICE WITH GATE
    4.
    发明申请
    MECHANISM FOR FORMING SEMICONDUCTOR DEVICE WITH GATE 有权
    用于形成具有盖的半导体器件的机构

    公开(公告)号:US20150129987A1

    公开(公告)日:2015-05-14

    申请号:US14080313

    申请日:2013-11-14

    CPC classification number: H01L29/7833 H01L29/0649 H01L29/6659

    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate.

    Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括半导体衬底和半导体衬底中的隔离结构,并围绕半导体衬底的有源区。 半导体器件还包括半导体衬底上的栅极,并且栅极具有在有源区上方的中间部分和连接到中间部分的两个端部,并且端部在隔离结构上方。 半导体器件还包括隔离结构上的支撑膜,并覆盖隔离结构和栅极的至少一个端部。 支撑膜暴露栅极的有源区域和中间部分。

    METHOD OF FORMING SEMICONDUCTOR DEVICE WITH GATE

    公开(公告)号:US20200295188A1

    公开(公告)日:2020-09-17

    申请号:US16892458

    申请日:2020-06-04

    Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate. The method includes forming a gate over the semiconductor substrate. The method includes forming a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure, the support film conformally covers a first portion of a top surface and a second portion of a first sidewall of the gate, the top surface faces away from the semiconductor substrate, the support film and a topmost surface of the active region do not overlap with each other, and the topmost surface faces the gate. The method includes after forming the support film, forming lightly doped regions in the semiconductor substrate and at two opposite sides of the gate.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20190165126A1

    公开(公告)日:2019-05-30

    申请号:US16180623

    申请日:2018-11-05

    Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

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