公开(公告)号：US09871100B2

公开(公告)日：2018-01-16

申请号：US14812864

申请日：2015-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming Lin ,  Shiu-Ko Jangjian ,  Chun-Che Lin ,  Ying-Lang Wang ,  Wei-Ken Lin ,  Chuan-Pu Liu

IPC: H01L29/06 ,  H01L27/08 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/785

Abstract: A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation structure is disposed in the trench. The liner layer is disposed between the substrate and the isolation structure. The liner layer includes nitrogen, and the liner layer has spatially various nitrogen concentration.

公开(公告)号：US11522001B2

公开(公告)日：2022-12-06

申请号：US17078948

申请日：2020-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiu-Ko Jangjian ,  Chih-Nan Wu ,  Chun-Che Lin ,  Yu-Ku Lin

IPC: H01L27/146

Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The plurality of photo sensitive regions are in the semiconductor substrate. The dielectric layer is on a backside surface of the semiconductor substrate facing away from the plurality of photo sensitive regions. The grid structure is on a backside surface of the dielectric layer facing away from the semiconductor substrate. The grid structure includes a plurality of grid lines spaced from each other. The plurality of convex dielectric lenses are alternately arranged with the plurality of grid lines of the grid structure on the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are lower than top ends of the plurality of grid lines of the grid structure.

公开(公告)号：US09985133B2

公开(公告)日：2018-05-29

申请号：US15332875

申请日：2016-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiu-Ko Jangjian ,  Chi-Cherng Jeng ,  Chih-Nan Wu ,  Chun-Che Lin ,  Ting-Chun Wang

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/161 ,  H01L29/20

CPC classification number: H01L29/7851 ,  H01L21/02274 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

公开(公告)号：US09824943B2

公开(公告)日：2017-11-21

申请号：US15082399

申请日：2016-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming Lin ,  Wei-Ken Lin ,  Shiu-Ko Jangjian ,  Chun-Che Lin

IPC: H01L21/762 ,  H01L21/66 ,  H01L21/3115 ,  H01L29/78

CPC classification number: H01L22/26 ,  H01L21/31105 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L22/12 ,  H01L29/7846 ,  H01L29/785

Abstract: A semiconductor structure with a stop layer for planarization process therein and a method for forming the same is disclosed. The method includes the steps of: forming a trench in a substrate and between active areas; filling the trench with isolation layer; doping the isolation layer with an element to form a doped isolation region; annealing the doped isolation region; and planarizing the annealed and doped isolation region and measuring a planarization depth thereof. The coefficients of thermal expansion (CTEs) of the stop layer, the dielectric layer, and the active area are different.

公开(公告)号：US12272708B2

公开(公告)日：2025-04-08

申请号：US18075323

申请日：2022-12-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiu-Ko Jangjian ,  Chih-Nan Wu ,  Chun-Che Lin ,  Yu-Ku Lin

IPC: H01L27/146

Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The photo sensitive regions are in the semiconductor substrate. The dielectric layer is over a backside surface of the semiconductor substrate. The grid structure is over a backside surface of the dielectric layer. The grid structure includes a plurality of grid lines. Each of the grid lines comprises a lower portion and an upper portion forming an interface with the lower portion. The convex dielectric lenses are alternately arranged with the grid lines over the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are higher than an interface between the upper portion and the lower portion of each of the grid lines.

公开(公告)号：US10957545B2

公开(公告)日：2021-03-23

申请号：US16206788

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming Lin ,  Shiu-Ko Jangjian ,  Chun-Che Lin

IPC: H01L21/285 ,  H01L21/28 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

Abstract: A method includes etching a dummy gate to form an opening. A gate dielectric layer is deposited in the opening. A blocking layer is deposited over the gate dielectric layer, wherein the blocking layer has a bottom portion over a bottom of the opening and a sidewall portion over a sidewall of the opening. An adhesive layer is deposited over the bottom portion of the blocking layer. A metal layer is deposited over the adhesive layer, wherein the metal layer is in contact with the sidewall portion of the blocking layer.

公开(公告)号：US10818716B2

公开(公告)日：2020-10-27

申请号：US16525372

申请日：2019-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiu-Ko Jangjian ,  Chih-Nan Wu ,  Chun-Che Lin ,  Yu-Ku Lin

IPC: H01L27/146

Abstract: An image sensor device includes a substrate, a pixel circuit, a dielectric structure, a photo sensitive element, a grid, and a convex dielectric lens. The substrate has a first side and a second side opposite to the first side. The pixel circuit is disposed on the first side of the substrate. The dielectric structure is disposed on the second side of the substrate. The photo sensitive element is disposed between the pixel circuit and the dielectric structure. The grid is disposed on the dielectric structure. The convex dielectric lens is disposed on the dielectric structure. The convex dielectric lens has a convex side. A topmost of the convex side is above an interface between the dielectric structure and the grid.

公开(公告)号：US10367021B2

公开(公告)日：2019-07-30

申请号：US14109318

申请日：2013-12-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiu-Ko Jangjian ,  Chih-Nan Wu ,  Chun-Che Lin ,  Yu-Ku Lin

IPC: H01L27/146

Abstract: An image sensor device includes a substrate, a photo sensitive element, a first dielectric structure and a convex dielectric lens. The substrate has a first side and a second side opposite to the first side. The photo sensitive element is formed on the first side of the substrate for receiving incident light transmitted through the substrate. The first dielectric structure is formed on the second side of the substrate. At least one portion of the convex dielectric lens is located in the first dielectric structure. The convex dielectric lens has a convex side oriented toward the incident light and a planar side oriented toward the photo sensitive element.

公开(公告)号：US10312366B2

公开(公告)日：2019-06-04

申请号：US15663636

申请日：2017-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Ren Sun ,  Shiu-Ko Jangjian ,  Kun-Ei Chen ,  Chun-Che Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/768

Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.

公开(公告)号：US09722076B2

公开(公告)日：2017-08-01

申请号：US14839932

申请日：2015-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Ren Sun ,  Shiu-Ko Jangjian ,  Kun-Ei Chen ,  Chun-Che Lin

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7831 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/823437 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions disposed in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.