公开(公告)号：US20160079239A1

公开(公告)日：2016-03-17

申请号：US14485541

申请日：2014-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Chi WANG ,  Chien-Chih LEE ,  Tien-Wei CHIANG ,  Ching-Wei TSAI ,  Chih-Ching WANG ,  Jon-Hsu HO ,  Wen-Hsing HSIEH

IPC: H01L27/088 ,  H01L29/45 ,  H01L29/06 ,  H01L21/31 ,  H01L29/66 ,  H01L21/283 ,  H01L21/306 ,  H01L21/768 ,  H01L29/78 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/76897 ,  H01L21/823487 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.

Abstract translation: 串联连接的晶体管结构包括第一源极，第一沟道 - 漏极结构，第二沟道 - 漏极结构，栅极电介质层，栅极，第一漏极焊盘和第二漏极焊盘。 第一个来源是在一个基板上。 第一沟道 - 漏极结构在第一源极上并且包括第一沟道和第一漏极。 第二沟道 - 漏极结构在第一源极上并且基本上平行于第一沟道 - 漏极结构并且包括第二沟道和第二漏极。 栅介质层围绕第一通道和第二通道。 栅极围绕栅介质层。 第一个漏极焊盘是与第一个漏极接触的。 第二漏极焊盘与第二漏极接触，其中第一漏极焊盘和第二漏极焊盘彼此分离。

公开(公告)号：US20140103438A1

公开(公告)日：2014-04-17

申请号：US14108391

申请日：2013-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching WANG ,  Jon-Hsu HO ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH ,  Tsung-Hsing YU ,  Yi-Ming SHEU ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L29/78

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.

Abstract translation: 一种多栅半导体器件及其制造方法。 形成多栅半导体器件，其包括形成在具有第一掺杂剂类型的半导体衬底上的第一晶体管的第一鳍。 第一晶体管具有第一掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一掺杂剂型半导体衬底上的第二晶体管的第二鳍。 第二晶体管具有第二掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一鳍片的沟道区域上的第二掺杂剂类型的栅极电极层和形成在第二鳍片的沟道区域上的第一掺杂剂类型的栅极电极层。

公开(公告)号：US20230369402A1

公开(公告)日：2023-11-16

申请号：US18181085

申请日：2023-03-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching WANG ,  Wen-Hsing HSIEH

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66439

Abstract: The present disclosure describes a semiconductor device having an asymmetric source/drain (S/D) design. The semiconductor device includes multiple semiconductor layers on a substrate, a gate structure wrapped around the multiple semiconductor layers, an inner spacer structure between the multiple semiconductor layers and in contact with a first side of the gate structure, and an epitaxial layer in contact with a second side of the gate structure. The second side is opposite to the first side.

公开(公告)号：US20220093743A1

公开(公告)日：2022-03-24

申请号：US17027302

申请日：2020-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Ching WANG ,  Wei-Yang LEE ,  Ming-Chang WEN ,  Jo-Tzu HUNG ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Embodiments of the present disclosure provide semiconductor device structures having at least one T-shaped stacked nanosheet transistor to provide increased effective conductive area across the channel regions. In one embodiment, the semiconductor device structure includes a first channel layer formed of a first material, wherein the first channel layer has a first width, and a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer and the second channel layer, and a gate electrode layer disposed on the gate dielectric layer.

公开(公告)号：US20160260713A1

公开(公告)日：2016-09-08

申请号：US15158462

申请日：2016-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Chi WANG ,  Chien-Chih LEE ,  Tien-Wei CHIANG ,  Ching-Wei TSAI ,  Chih-Ching WANG ,  Jon-Hsu HO ,  Wen-Hsing HSIEH

IPC: H01L27/088 ,  H01L21/768 ,  H01L23/528 ,  H01L29/423 ,  H01L29/06 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L21/283 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/76897 ,  H01L21/823487 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.

Abstract translation: 串联连接的晶体管结构包括第一源极，第一沟道 - 漏极结构，第二沟道 - 漏极结构，栅极电介质层，栅极，第一漏极焊盘和第二漏极焊盘。 第一个来源是在一个基板上。 第一沟道 - 漏极结构在第一源极上并且包括第一沟道和第一漏极。 第二沟道 - 漏极结构在第一源极上并且基本上平行于第一沟道 - 漏极结构并且包括第二沟道和第二漏极。 栅介质层围绕第一通道和第二通道。 栅极围绕栅介质层。 第一个漏极焊盘是与第一个漏极接触的。 第二漏极焊盘与第二漏极接触，其中第一漏极焊盘和第二漏极焊盘彼此分离。

公开(公告)号：US20150162334A1

公开(公告)日：2015-06-11

申请号：US14624782

申请日：2015-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jon-Hsu HO ,  Chih-Ching WANG ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH ,  Tsung-Hsing YU ,  Yi-Ming SHEU ,  Chih-Chieh YEH ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

Abstract translation: 形成包括半导体衬底的多栅极半导体器件。 多栅半导体器件还包括第一晶体管，其包括在半导体衬底之上延伸的第一鳍部。 第一晶体管具有形成在其中的第一沟道区。 第一沟道区域包括以第一掺杂剂类型的第一浓度掺杂的第一沟道区域部分和以第一掺杂剂类型的第二浓度掺杂的第二沟道区域部分。 第二浓度高于第一浓度。 第一晶体管还包括形成在第一沟道区上的第一栅电极层。 第一栅极电极层可以是第二掺杂剂类型。 第一掺杂剂类型可以是N型，第二掺杂剂类型可以是P型。 第二沟道区域部分可以形成在第一沟道区域部分上。