公开(公告)号：US12136600B2

公开(公告)日：2024-11-05

申请号：US17468886

申请日：2021-09-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chang Chen ,  Kun-Hsiang Lin ,  Cheng-Chien Li

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528

Abstract: The present disclosure describes a semiconductor structure including a TSV in contact with a substrate and a metal ring structure laterally surrounding the TSV. The metal ring structure includes one or more metal rings arranged as a stack and one or more metal vias interposed between two adjacent metal rings of the one or more metal rings. The metal ring structure is electrically coupled to the substrate through one or more conductive structures.

公开(公告)号：US20230361181A1

公开(公告)日：2023-11-09

申请号：US18353498

申请日：2023-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Chang ,  Chi-Wen Liu ,  Cheng-Chien Li ,  Hsin-Chieh Huang

IPC: H01L29/36 ,  H01L29/167 ,  H01L29/06 ,  H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/36 ,  H01L29/167 ,  H01L29/0657 ,  H01L29/785 ,  H01L21/26506 ,  H01L21/02532 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

公开(公告)号：US11049775B2

公开(公告)日：2021-06-29

申请号：US16455646

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ching Huang ,  Cheng-Chien Li ,  Wen-Li Chiu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423

Abstract: Provided is a semiconductor device including a first fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure over a first semiconductor fin and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer has a bar-shaped structure, the second layer has a U-shaped structure encapsulating sidewalls and a bottom surface of the first layer, and the first layer and the second layer include different materials. A method of manufacturing the semiconductor device is also provided.

公开(公告)号：US20200043809A1

公开(公告)日：2020-02-06

申请号：US16455646

申请日：2019-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ching Huang ,  Cheng-Chien Li ,  Wen-Li Chiu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423

Abstract: Provided is a semiconductor device including a first fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure over a first semiconductor fin and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer has a bar-shaped structure, the second layer has a U-shaped structure encapsulating sidewalls and a bottom surface of the first layer, and the first layer and the second layer include different materials. A method of manufacturing the semiconductor device is also provided.

公开(公告)号：US09647122B2

公开(公告)日：2017-05-09

申请号：US15154982

申请日：2016-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ming Chang ,  Chi-Wen Liu ,  Hsin-Chieh Huang ,  Cheng-Chien Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/36 ,  H01L29/06 ,  H01L29/49 ,  H01L29/40

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. A topmost location of the epitaxy structure has an n-type impurity concentration lower than an n-type impurity concentration of a location of the epitaxy structure below the topmost location.

公开(公告)号：US12237380B2

公开(公告)日：2025-02-25

申请号：US18353498

申请日：2023-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Chang ,  Chi-Wen Liu ,  Cheng-Chien Li ,  Hsin-Chieh Huang

IPC: H01L29/36 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/167 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

公开(公告)号：US12046566B2

公开(公告)日：2024-07-23

申请号：US17481003

申请日：2021-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Ku ,  Yao-Chun Chuang ,  Ching-Pin Lin ,  Cheng-Chien Li

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/58

CPC classification number: H01L23/585 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/564

Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.

公开(公告)号：US11749724B2

公开(公告)日：2023-09-05

申请号：US17329929

申请日：2021-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Chang ,  Chi-Wen Liu ,  Cheng-Chien Li ,  Hsin-Chieh Huang

IPC: H01L29/36 ,  H01L29/167 ,  H01L29/06 ,  H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/36 ,  H01L21/02532 ,  H01L21/26506 ,  H01L29/0657 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

公开(公告)号：US20220328429A1

公开(公告)日：2022-10-13

申请号：US17468886

申请日：2021-09-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chang CHEN ,  Kun-Hsiang Lin ,  Cheng-Chien Li

IPC: H01L23/58 ,  H01L23/48 ,  H01L21/768 ,  H01L23/528

Abstract: The present disclosure describes a semiconductor structure including a TSV in contact with a substrate and a metal ring structure laterally surrounding the TSV. The metal ring structure includes one or more metal rings arranged as a stack and one or more metal vias interposed between two adjacent metal rings of the one or more metal rings. The metal ring structure is electrically coupled to the substrate through one or more conductive structures.

公开(公告)号：US20190304842A1

公开(公告)日：2019-10-03

申请号：US15939304

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chien Li ,  Wei-Shuo Ho ,  Huang-Chao Chang ,  Wei-Zhe Jhang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: A method for forming a FinFET device is described. The method includes the following steps. A substrate is patterned to form fins. Dummy gate stack is formed on the substrate and over the fins, wherein the dummy gate stack may be formed by the following steps: a dummy layer is formed; a first etching step is performed on the dummy layer with a bromine containing etching gas to form a dummy strip; a second etching step is performed on the dummy strip with a chlorine containing etching gas to form the dummy gate stack. The dummy gate stack is replaced with a gate stack.