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公开(公告)号:US11929423B2
公开(公告)日:2024-03-12
申请号:US17347715
申请日:2021-06-15
发明人: Sebastian Meier , Helmut Rinck , Mike Mittelstaedt
IPC分类号: H01L29/66 , C01G55/00 , H01L21/02 , H01L21/263 , H01L21/28 , H01L21/285 , H01L21/311 , H01L21/3213 , H01L21/768 , H01L23/00 , H01L23/532 , H01L29/49 , H01L29/78 , H01L49/02 , H01L21/8238
CPC分类号: H01L29/665 , C01G55/00 , C01G55/004 , H01L21/02068 , H01L21/2633 , H01L21/28052 , H01L21/28518 , H01L21/31122 , H01L21/32134 , H01L21/32139 , H01L21/76885 , H01L21/76895 , H01L23/53242 , H01L24/00 , H01L28/24 , H01L29/4975 , H01L29/6659 , H01L29/7833 , H01L21/76834 , H01L21/823814 , H01L21/823835
摘要: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.
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公开(公告)号:US20220384252A1
公开(公告)日:2022-12-01
申请号:US17710139
申请日:2022-03-31
IPC分类号: H01L21/762
摘要: A device includes a die with a protective overcoat and a substrate, the substrate comprising a first region and a second region that are spaced apart. The device also includes an isolation dielectric between the protective overcoat and the die. A pre-metal dielectric (PMD) barrier is between the isolation dielectric and the substrate, the PMD barrier having a first region that contacts the first region of the substrate and a second region that contacts the second region of the substrate, the first region and the second region of the PMD barrier being spaced apart. A through trench filled with a polymer dielectric extends between the first region and the second region of the substrate, and between the first region and the second region of the PMD barrier to contact the isolation dielectric.
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公开(公告)号:US20220065811A1
公开(公告)日:2022-03-03
申请号:US17461975
申请日:2021-08-30
发明人: Sebastian Meier
IPC分类号: G01N27/414 , G01N27/02 , G01N1/38
摘要: In described examples, a biosensor device has a porous membrane with a test region that contains a test analyte. A sensor die has an ion sensing field effect transistor (ISFET) with an ion sensitive gate element located in an active sensor surface of the sensor die. The active sensor surface is in contact with the porous membrane test region. A controller is coupled to the ISFET and an interface module is coupled to the controller to provide a human readable test result.
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公开(公告)号:US20210242029A1
公开(公告)日:2021-08-05
申请号:US17234833
申请日:2021-04-20
发明人: Sebastian Meier , Helmut Rinck
IPC分类号: H01L21/306 , H01L21/308 , C23F1/44 , C23F1/30 , H01L21/24
摘要: There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.
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公开(公告)号:US20200303202A1
公开(公告)日:2020-09-24
申请号:US16897357
申请日:2020-06-10
IPC分类号: H01L21/311 , H01L21/02 , H01L21/3205 , H01L23/00 , G01N27/414
摘要: A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.
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6.
公开(公告)号:US20190304796A1
公开(公告)日:2019-10-03
申请号:US15936434
申请日:2018-03-27
IPC分类号: H01L21/311 , H01L21/02 , H01L21/3205 , H01L23/00 , G01N27/414
摘要: A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.
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公开(公告)号:US20210313179A1
公开(公告)日:2021-10-07
申请号:US17347715
申请日:2021-06-15
发明人: Sebastian Meier , Helmut Rinck , Mike Mittelstaedt
IPC分类号: H01L21/28 , H01L21/311 , C01G55/00 , H01L21/263 , H01L29/49 , H01L21/3213 , H01L21/02 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/285 , H01L23/00 , H01L49/02 , H01L23/532
摘要: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.
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公开(公告)号:US11069530B2
公开(公告)日:2021-07-20
申请号:US16688060
申请日:2019-11-19
发明人: Sebastian Meier , Helmut Rinck , Mike Mittelstaedt
IPC分类号: H01L21/44 , H01L21/28 , H01L21/311 , C01G55/00 , H01L21/263 , H01L29/49 , H01L21/3213 , H01L21/02 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/285 , H01L23/00 , H01L49/02 , H01L23/532 , H01L21/8238
摘要: A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.
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公开(公告)号:US20200083050A1
公开(公告)日:2020-03-12
申请号:US16688060
申请日:2019-11-19
发明人: Sebastian Meier , Helmut Rinck , Mike Mittelstaedt
IPC分类号: H01L21/28 , H01L29/49 , H01L21/263 , C01G55/00 , H01L21/311 , H01L23/532 , H01L21/768 , H01L29/66 , H01L49/02 , H01L23/00 , H01L21/285 , H01L21/3213 , H01L29/78 , H01L21/02
摘要: A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.
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公开(公告)号:US20180204734A1
公开(公告)日:2018-07-19
申请号:US15714169
申请日:2017-09-25
发明人: Sebastian Meier , Helmut Rinck , Mike Mittelstaedt
IPC分类号: H01L21/311 , H01L21/263
CPC分类号: H01L21/28052 , C01G55/00 , C01G55/004 , H01L21/02068 , H01L21/2633 , H01L21/28518 , H01L21/31122 , H01L21/32134 , H01L21/32139 , H01L21/76834 , H01L21/76885 , H01L21/76895 , H01L21/823814 , H01L21/823835 , H01L23/53242 , H01L24/00 , H01L28/24 , H01L29/4975 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要: A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.
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