公开(公告)号：US12205822B2

公开(公告)日：2025-01-21

申请号：US17450123

申请日：2021-10-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Cheng Chao ,  Hsin-Chieh Huang ,  Yu-Wen Wang

IPC: H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423

Abstract: Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.

公开(公告)号：US11854993B2

公开(公告)日：2023-12-26

申请号：US17749125

申请日：2022-05-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Yen Chiu ,  Ching-Fu Chang ,  Hsin-Chieh Huang

IPC: H01L23/538 ,  H01L23/66 ,  H01L49/02 ,  H01L23/31 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L27/146 ,  H01L23/522

CPC classification number: H01L23/5389 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/66 ,  H01L28/10 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5225 ,  H01L24/20 ,  H01L24/96 ,  H01L27/14618 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/023 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/97

Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.

公开(公告)号：US11069614B2

公开(公告)日：2021-07-20

申请号：US16870458

申请日：2020-05-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsi-Kuei Cheng ,  Chih-Kang Han ,  Ching-Fu Chang ,  Hsin-Chieh Huang

IPC: H01L23/522 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.

公开(公告)号：US20200027963A1

公开(公告)日：2020-01-23

申请号：US16583805

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Sheng Li ,  Hsin-Chieh Huang ,  Chi-Wen Liu

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/31 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L27/108 ,  H01L29/417 ,  H01L27/092 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/467 ,  H01L21/302 ,  H01L21/8238 ,  H01L21/461 ,  H01L21/84 ,  H01L21/465

Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.

公开(公告)号：US20180108742A1

公开(公告)日：2018-04-19

申请号：US15817779

申请日：2017-11-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Ming Chang ,  Chi-Wen Liu ,  Cheng-Chien Li ,  Hsin-Chieh Huang

IPC: H01L29/36 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02 ,  H01L29/06 ,  H01L29/167 ,  H01L21/265

CPC classification number: H01L29/36 ,  H01L21/02532 ,  H01L21/26506 ,  H01L29/0657 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

公开(公告)号：US09922896B1

公开(公告)日：2018-03-20

申请号：US15390226

申请日：2016-12-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsi-Kuei Cheng ,  Ching Fu Chang ,  Chih-Kang Han ,  Hsin-Chieh Huang

IPC: H01L21/4763 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/78 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/288 ,  H01L23/48 ,  H01L21/683

CPC classification number: H01L21/6835 ,  H01L21/288 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/20 ,  H01L24/94 ,  H01L25/065 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442

Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

公开(公告)号：US20170323840A1

公开(公告)日：2017-11-09

申请号：US15254472

申请日：2016-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Yen Chiu ,  Hsin-Chieh Huang ,  Ching Fu Chang

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/3105 ,  H01L21/78 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/3107 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76895 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/05 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2224/214

Abstract: A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.

公开(公告)号：US20210257479A1

公开(公告)日：2021-08-19

申请号：US17021640

申请日：2020-09-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Che-Lun Chang ,  Shiao-Shin Cheng ,  Ji-Yin Tsai ,  Yu-Lin Tsai ,  Hsin-Chieh Huang ,  Ming-Yuan Wu ,  Jiun-Ming Kuo ,  Ming-Jie Huang ,  Yu-Wen Wang ,  Che-Yuan Hsu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/08 ,  H01L29/78

Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.

公开(公告)号：US10964801B2

公开(公告)日：2021-03-30

申请号：US16583805

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Sheng Li ,  Hsin-Chieh Huang ,  Chi-Wen Liu

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/31 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L27/108 ,  H01L29/417 ,  H01L27/092 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/467 ,  H01L21/302 ,  H01L21/8238 ,  H01L21/461 ,  H01L21/84 ,  H01L21/465 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.

公开(公告)号：US20200035564A1

公开(公告)日：2020-01-30

申请号：US16593287

申请日：2019-10-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Sheng Li ,  Hsin-Chieh Huang ,  Chi-Wen Liu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/311

Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.