公开(公告)号：US12040364B2

公开(公告)日：2024-07-16

申请号：US18297868

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsueh-Wen Tsau ,  Chun-I Wu ,  Ziwei Fang ,  Huang-Lin Chao ,  I-Ming Chang ,  Chung-Liang Cheng ,  Chih-Cheng Lin

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/768 ,  H01L23/532 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L23/522 ,  H01L29/06

CPC classification number: H01L29/401 ,  H01L21/28247 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/28088 ,  H01L21/28568 ,  H01L23/5226 ,  H01L29/0673

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate, the silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer includes an oxide material.

公开(公告)号：US11860532B2

公开(公告)日：2024-01-02

申请号：US17815041

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Chang Lee ,  Ping-Hsun Lin ,  Chih-Cheng Lin ,  Chia-Jen Chen

IPC: G03F1/44 ,  G03F1/84 ,  G03F1/42 ,  G03F1/54 ,  G03F1/72 ,  G03F1/76 ,  G03F7/20 ,  G03F1/22 ,  H01L21/027 ,  G03F1/78

CPC classification number: G03F1/44 ,  G03F1/42 ,  G03F1/84 ,  G03F1/22 ,  G03F1/54 ,  G03F1/72 ,  G03F1/76 ,  G03F1/78 ,  G03F7/2004 ,  H01L21/0274

Abstract: A method of making a semiconductor device includes defining a pattern including a plurality of sub-patterns on the photomask in the pattern region based on the identifying information. The defining of the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns, or rotating the first sub-pattern about an axis perpendicular to a top surface of the photomask relative to the second sub-pattern.

公开(公告)号：US10274819B2

公开(公告)日：2019-04-30

申请号：US14615185

申请日：2015-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pei-Cheng Hsu ,  Chih-Tsung Shih ,  Jeng-Horng Chen ,  Chih-Cheng Lin ,  Hsin-Chang Lee ,  Shinn-Sheng Yu ,  Ta-Cheng Lien ,  Anthony Yen

IPC: B44C1/22 ,  C25F3/00 ,  C23F1/00 ,  C23F3/00 ,  G03F1/62

Abstract: A method for fabricating a pellicle for EUV lithography processes includes placing a hard mask in contact with a surface of a substrate. In some embodiments, the hard mask is configured to pattern the surface of the substrate to include a first region and a second region surrounding the first region. By way of example, while the mask in positioned in contact with the substrate, an etch process of the substrate is performed to etch the first and second regions into the substrate. Thereafter, an excess substrate region is removed so as to separate the etched first region from the excess substrate region. In various embodiments, the etched and separated first region serves as a pellicle for an extreme ultraviolet (EUV) lithography process.

公开(公告)号：US20170205705A1

公开(公告)日：2017-07-20

申请号：US14996966

申请日：2016-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jeng-Shin Ma ,  Tsiao-Chen Wu ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chih-Cheng Lin ,  Yun-Yue Lin

IPC: G03F1/64

CPC classification number: G03F1/64 ,  G03F1/62

Abstract: A method for manufacturing a pellicle includes: providing a supporting substrate; forming an oxide layer over the supporting substrate; forming a metal layer over the oxide layer; forming a graphene layer over the metal layer; and removing at least a portion of the supporting substrate and the oxide layer. An associated method includes: providing a supporting substrate; forming a first silicon carbide (SiC) layer or a diamond layer over the supporting substrate; forming a graphene layer over the SiC layer or the diamond layer; and removing at least a portion of the supporting substrate and the first silicon carbide (SiC) layer or the diamond layer; wherein the pellicle is at least partially transparent to extreme ultraviolet (EUV) radiation. An associated pellicle is also disclosed.

公开(公告)号：US20160231647A1

公开(公告)日：2016-08-11

申请号：US14615185

申请日：2015-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pei-Cheng Hsu ,  Chih-Tsung Shih ,  Jeng-Horng Chen ,  Chih-Cheng Lin ,  Hsin-Chang Lee ,  Shinn-Sheng Yu ,  Ta-Cheng Lien ,  Anthony Yen

IPC: G03F1/62

CPC classification number: G03F1/62

Abstract: A method for fabricating a pellicle for EUV lithography processes includes placing a hard mask in contact with a surface of a substrate. In some embodiments, the hard mask is configured to pattern the surface of the substrate to include a first region and a second region surrounding the first region. By way of example, while the mask in positioned in contact with the substrate, an etch process of the substrate is performed to etch the first and second regions into the substrate. Thereafter, an excess substrate region is removed so as to separate the etched first region from the excess substrate region. In various embodiments, the etched and separated first region serves as a pellicle for an extreme ultraviolet (EUV) lithography process.

Abstract translation: 用于制造用于EUV光刻工艺的防护薄膜的方法包括将硬掩模放置成与基底的表面接触。 在一些实施例中，硬掩模被配置成图案化衬底的表面以包括围绕第一区域的第一区域和第二区域。 作为示例，当定位成与衬底接触的掩模时，执行衬底的蚀刻工艺以将第一和第二区域蚀刻到衬底中。 此后，去除过量的衬底区域，以将蚀刻的第一区域与过剩衬底区域分离。 在各种实施例中，蚀刻和分离的第一区域用作极紫外（EUV）光刻工艺的防护薄膜。

公开(公告)号：US11422466B2

公开(公告)日：2022-08-23

申请号：US17335944

申请日：2021-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Chang Lee ,  Ping-Hsun Lin ,  Chih-Cheng Lin ,  Chia-Jen Chen

IPC: G03F7/20 ,  G03F1/44 ,  G03F1/54 ,  G03F1/72 ,  G03F1/76 ,  G03F1/84 ,  G03F1/22 ,  H01L21/027 ,  G03F1/78 ,  G03F1/42

Abstract: A method of making a semiconductor device includes forming at least one fiducial mark on a photomask outside of a pattern region of the photomask, and the at least one fiducial mark includes identifying information for the photomask. The method includes defining a pattern including a plurality of sub-patterns on the photomask in the pattern region based on the identifying information. The defining of the pattern includes defining a first sub-pattern of the plurality of sub-patterns having a first spacing from a second sub-pattern of the plurality of sub-patterns, wherein the first spacing is different from a second spacing between the second sub-pattern and a third sub-pattern of the plurality of sub-patterns, or rotating the first sub-pattern about an axis perpendicular to a top surface of the photomask relative to the second sub-pattern. The method includes transferring the pattern from the photomask to a wafer.

公开(公告)号：US11294274B2

公开(公告)日：2022-04-05

申请号：US16741342

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Amo Chen ,  Yun-Yue Lin ,  Ta-Cheng Lien ,  Hsin-Chang Lee ,  Chih-Cheng Lin ,  Jeng-Horng Chen

IPC: G03F1/64 ,  G03F1/62 ,  G03F1/22 ,  G03F7/20 ,  H01L21/027

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a porous pellicle frame, a mask with a patterned surface, a first thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame, and a second thermal conductive adhesive layer that secures the porous pellicle frame to the mask.

公开(公告)号：US11042084B2

公开(公告)日：2021-06-22

申请号：US16399843

申请日：2019-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Chang Lee ,  Chia-Jen Chen ,  Chih-Cheng Lin ,  Ping-Hsun Lin

IPC: G03F1/44 ,  G03F1/84 ,  G03F1/42 ,  G03F1/54 ,  G03F1/72 ,  G03F1/76 ,  G03F7/20 ,  G03F1/22 ,  G03F1/78 ,  H01L21/027

Abstract: A photomask includes a pattern region and a plurality of defects in the pattern region. The photomask further includes a first fiducial mark outside of the pattern region, wherein the first fiducial mark includes identifying information for the photomask, the first fiducial mark has a first size and a first shape. The photomask further includes a second fiducial mark outside of the pattern region. The second fiducial mark has a second size different from the first size, or a second shape different from the first shape.

公开(公告)号：US09864270B2

公开(公告)日：2018-01-09

申请号：US14996966

申请日：2016-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jeng-Shin Ma ,  Tsiao-Chen Wu ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chih-Cheng Lin ,  Yun-Yue Lin

IPC: G03F1/62 ,  G03F1/64

CPC classification number: G03F1/64 ,  G03F1/62

Abstract: A method for manufacturing a pellicle includes: providing a supporting substrate; forming an oxide layer over the supporting substrate; forming a metal layer over the oxide layer; forming a graphene layer over the metal layer; and removing at least a portion of the supporting substrate and the oxide layer. An associated method includes: providing a supporting substrate; forming a first silicon carbide (SiC) layer or a diamond layer over the supporting substrate; forming a graphene layer over the SiC layer or the diamond layer; and removing at least a portion of the supporting substrate and the first silicon carbide (SiC) layer or the diamond layer; wherein the pellicle is at least partially transparent to extreme ultraviolet (EUV) radiation. An associated pellicle is also disclosed.

公开(公告)号：US11626493B2

公开(公告)日：2023-04-11

申请号：US17345382

申请日：2021-06-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsueh-Wen Tsau ,  Chun-I Wu ,  Ziwei Fang ,  Huang-Lin Chao ,  I-Ming Chang ,  Chung-Liang Cheng ,  Chih-Cheng Lin

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L23/532 ,  H01L29/66 ,  H01L23/522 ,  H01L21/285 ,  H01L29/06

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate. The silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer is thinner than the second metal-containing layer.