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    Apparatus for Three Dimensional Integrated Circuit Testing
    2.
    发明申请
    Apparatus for Three Dimensional Integrated Circuit Testing 有权
    三维集成电路测试装置

    公开(公告)号：US20140176165A1

    公开(公告)日：2014-06-26

    申请号：US13724004

    申请日：2012-12-21

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Mill-Jer Wang ,  Ching-Nen Peng ,  Hung-Chih Lin ,  Hao Chen ,  Chung-Han Huang ,  Chung-Sheng Yuan ,  Ching-Fang Chen ,  Wen-Wen Hsieh ,  Meng-Lin Chung

    IPC: G01R31/26

    CPC classification number: G01R31/2889 ,  G01R1/07378

    Abstract: A three-dimensional integrated circuit testing apparatus comprises a probe card configured to couple a device-under-test of a three-dimensional integrated circuit with an automatic testing equipment board having a plurality of testing modules, wherein the probe card comprises a plurality of known good dies of the three-dimensional integrated circuit, a plurality of interconnects of the three-dimensional integrated circuit and a plurality of probe contacts, wherein the probe contacts are configured to couple the probe card with testing contacts of the device-under-test of the three-dimensional integrated circuit.

    Abstract translation: 三维集成电路测试装置包括：探针卡，被配置为将三维集成电路的测试装置与具有多个测试模块的自动测试设备板耦合，其中所述探针卡包括多个已知的 三维集成电路的良好裸片，三维集成电路的多个互连和多个探针触点，其中探针触点被配置为将探针卡与被测器件的测试触点耦合 三维集成电路。

    INTEGRATED FAN-OUT PILLAR PROBE SYSTEM
    7.
    发明申请
    INTEGRATED FAN-OUT PILLAR PROBE SYSTEM 有权
    集成扇出式探头系统

    公开(公告)号：US20160077147A1

    公开(公告)日：2016-03-17

    申请号：US14488852

    申请日：2014-09-17

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Mill-Jer Wang ,  Ching-Nen Peng ,  Hung-Chih Lin ,  Hao Chen ,  Mincent Lee ,  Chen-Hung Tien ,  Chang Chia How

    IPC: G01R31/26 ,  G01R1/067 ,  G01R31/28

    CPC classification number: G01R31/2893 ,  G01R3/00 ,  G01R31/2891 ,  G01R31/2894

    Abstract: Disclosed herein is a method of probe testing dies, the method comprising loading a wafer having a first die and a second die into a prober and bringing probes of the prober into contact with first contact pads of the first die according to first probe parameters. A first probe contact test of first values of the contact between the probes and the first contact pads is performed, and a die test of the first die is performed after performing the probe contact test. Results of the die test and results of the probe contact test are saved and second probe parameters are automatically generated based on at least the results of the first probe contact test.

    Abstract translation: 本文公开了一种探针测试模具的方法，所述方法包括将具有第一管芯和第二管芯的晶片加载到探测器中，并使探针的探针根据第一探针参数与第一管芯的第一接触焊盘接触。 执行探针与第一接触焊盘之间的接触的第一值的第一探针接触测试，并且在执行探针接触测试之后执行第一裸片的模头测试。 保存模具试验结果和探针接触试验结果，至少基于第一次探针接触试验的结果自动生成第二探头参数。

    3D IC Testing Apparatus
    9.
    发明申请
    3D IC Testing Apparatus 审中-公开
    3D IC测试仪器

    公开(公告)号：US20150087089A1

    公开(公告)日：2015-03-26

    申请号：US14561442

    申请日：2014-12-05

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Mill-Jer Wang ,  Chih-Chia Chen ,  Hung-Chih Lin ,  Ching-Nen Peng ,  Hao Chen

    IPC: G01R31/28 ,  G01R1/073 ,  H01L21/66

    CPC classification number: G01R31/2884 ,  G01R1/07378 ,  G01R31/2834 ,  G01R31/2886 ,  H01L22/14 ,  Y02P80/30

    Abstract: A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup.

    Abstract translation: 一种方法包括将具有多个探针的测试装置连接到具有多个通孔的被测器件，其中探针与被测器件的相应通孔对准，并通过导电通路进行多次通孔电特性测试 包括通孔，探针和多个导电装置，每个导电装置连接两个相邻的探针，其中导电装置处于测试装置中。

    METHOD AND APPARATUS OF WAFER TESTING
    10.
    发明申请
    METHOD AND APPARATUS OF WAFER TESTING 有权
    测试方法和设备

    公开(公告)号：US20140361804A1

    公开(公告)日：2014-12-11

    申请号：US13915409

    申请日：2013-06-11

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Mill-Jer Wang ,  Ching-Nen Peng ,  Hung-Chih Lin ,  Hao Chen ,  Shang-Ju Lee

    IPC: G01R1/073

    CPC classification number: G01R31/318511 ,  G01R31/2889 ,  G01R31/318513

    Abstract: A system for testing a wafer includes a probe card and a wafer. The probe card includes at least one first probe site and at least one second probe site. The wafer includes a plurality of dies. The at least one first probe site is arranged for a first test, and the at least one second probe site is arranged for a second test. Each of the plurality of dies corresponds to first probe pads and second probe pads. Each of the at least one first probe site is arranged to touch the first probe pads of each of the plurality of dies. Each of the at least one second probe site is arranged to touch the second probe pads of each of the plurality of dies.

    Abstract translation: 用于测试晶片的系统包括探针卡和晶片。 探针卡包括至少一个第一探针位点和至少一个第二探针位点。 晶片包括多个管芯。 所述至少一个第一探针位置被布置用于第一测试，并且所述至少一个第二探针位置被布置用于第二测试。 多个管芯中的每一个对应于第一探针焊盘和第二探针焊盘。 所述至少一个第一探针位置中的每一个被布置成接触所述多个管芯中的每一个的所述第一探针焊盘。 所述至少一个第二探针位置中的每一个被布置成接触所述多个管芯中的每一个的所述第二探针焊盘。

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