Invention Grant
- Patent Title: 3D IC testing apparatus
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Application No.: US14561442Application Date: 2014-12-05
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Publication No.: US09671457B2Publication Date: 2017-06-06
- Inventor: Mill-Jer Wang , Chih-Chia Chen , Hung-Chih Lin , Ching-Nen Peng , Hao Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: G01R31/20
- IPC: G01R31/20 ; G01R31/28 ; G01R1/073 ; H01L21/66

Abstract:
A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup.
Public/Granted literature
- US20150087089A1 3D IC Testing Apparatus Public/Granted day:2015-03-26
Information query