知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.02 seconds)

    MEMORY DEVICE
    1.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20220223651A1

    公开(公告)日：2022-07-14

    申请号：US17709845

    申请日：2022-03-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chieh-Fei CHIU ,  Yong-Shiuan TSAIR ,  Wen-Ting CHU ,  Yu-Wen LIAO ,  Chin-Yu MEI ,  Po-Hao TSENG

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

    MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    3.
    发明申请
    MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开

    公开(公告)号：US20180358409A1

    公开(公告)日：2018-12-13

    申请号：US15617019

    申请日：2017-06-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ching-Pei HSIEH ,  Hsia-Wei CHEN ,  Yu-Wen LIAO

    IPC: H01L27/24 ,  H01L23/528 ,  H01L23/522 ,  H01L45/00

    Abstract: A memory device includes a first inter-layer dielectric layer, plural conductive features, plural memory structures, a filler, and a second inter-layer dielectric layer. The conductive features are embedded in the first inter-layer dielectric layer. The memory structures are respectively over the conductive features. The filler is in between the memory structures. The second inter-layer dielectric layer is over the filler and the memory structures, and the second inter-layer dielectric layer and the filler form an interface, in which the interface extends from one of the memory structures to another of the memory structures.

    MEMORY CELLS BREAKDOWN PROTECTION
    5.
    发明申请
    MEMORY CELLS BREAKDOWN PROTECTION 有权
    存储器电池断开保护

    公开(公告)号：US20150092471A1

    公开(公告)日：2015-04-02

    申请号：US14041916

    申请日：2013-09-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wen-Chun YOU ,  Kuo-Chi TU ,  Chih-Yang CHANG ,  Hsia-Wei CHEN ,  Yu-Wen LIAO ,  Chin-Chieh YANG ,  Sheng-Hung SHIH ,  Wen-Ting CHU

    IPC: G11C13/00

    CPC classification number: G11C13/003 ,  G11C13/0002 ,  G11C13/0059 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2213/79

    Abstract: A method is disclosed that includes the operations outlined below. A first voltage is applied to a gate of an access transistor of each of a row of memory cells during a reset operation, wherein a first source/drain of the access transistor is electrically connected to a first electrode of a resistive random access memory (RRAM) device in the same memory cell. An inhibition voltage is applied to a second electrode of the RRAM device or to a second source/drain of the access transistor of each of a plurality of unselected memory cells when the first voltage is applied to the gate of the access transistor.

    Abstract translation: 公开了一种包括以下概述的操作的方法。 在复位操作期间，第一电压被施加到每行存储单元的存取晶体管的栅极，其中存取晶体管的第一源极/漏极电连接到电阻随机存取存储器（RRAM）的第一电极 ）设备在同一个存储单元中。 当第一电压被施加到存取晶体管的栅极时，抑制电压被施加到RRAM器件的第二电极或多个未选择存储器单元中的每一个的存取晶体管的第二源极/漏极。

Patent Agency Ranking