公开(公告)号：US20220223651A1

公开(公告)日：2022-07-14

申请号：US17709845

申请日：2022-03-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Fei CHIU ,  Yong-Shiuan TSAIR ,  Wen-Ting CHU ,  Yu-Wen LIAO ,  Chin-Yu MEI ,  Po-Hao TSENG

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

公开(公告)号：US20220102428A1

公开(公告)日：2022-03-31

申请号：US17032155

申请日：2020-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Fei CHIU ,  Wen-Ting CHU ,  Yong-Shiuan TSAIR ,  Yu-Wen LIAO ,  Chih-Yang CHANG ,  Chin-Chieh YANG

IPC: H01L27/24 ,  H01L27/1159 ,  H01L27/11592 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L45/00

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

公开(公告)号：US20230380190A1

公开(公告)日：2023-11-23

申请号：US18361483

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Fei CHIU ,  Wen-Ting CHU ,  Yong-Shiuan TSAIR ,  Yu-Wen LIAO ,  Chih-Yang CHANG ,  Chin-Chieh YANG

IPC: H10B63/00 ,  H10B51/30 ,  H10B51/40 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/30 ,  H10B51/30 ,  H10B51/40 ,  H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/068 ,  H10N70/231 ,  H10N70/253 ,  H10N70/841

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

公开(公告)号：US20190157281A1

公开(公告)日：2019-05-23

申请号：US16204840

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang YANG ,  Yong-Shiuan TSAIR ,  Po-Wei LIU ,  Hung-Ling SHIH ,  Yu-Ling HSU ,  Chieh-Fei CHIU ,  Wen-Tuo HUANG

IPC: H01L27/11521 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L27/11521 ,  H01L29/40114 ,  H01L29/42344 ,  H01L29/78

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US20180061847A1

公开(公告)日：2018-03-01

申请号：US15272067

申请日：2016-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Ling SHIH ,  Chieh-Fei CHIU ,  Po-Wei LIU ,  Tsun-Kai TSAO ,  Wen-Tuo HUANG ,  Yu-Ling HSU ,  Yong-Shiuan TSAIR

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

Abstract: A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.

公开(公告)号：US20210225857A1

公开(公告)日：2021-07-22

申请号：US17226348

申请日：2021-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang YANG ,  Yong-Shiuan TSAIR ,  Po-Wei LIU ,  Hung-Ling SHIH ,  Yu-Ling HSU ,  Chieh-Fei CHIU ,  Wen-Tuo HUANG

IPC: H01L27/11521 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US20200161317A1

公开(公告)日：2020-05-21

申请号：US16748584

申请日：2020-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang YANG ,  Yong-Shiuan TSAIR ,  Po-Wei LIU ,  Hung-Ling SHIH ,  Yu-Ling HSU ,  Chieh-Fei CHIU ,  Wen-Tuo HUANG

IPC: H01L27/11521 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US20180315764A1

公开(公告)日：2018-11-01

申请号：US15498743

申请日：2017-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang YANG ,  Hung-Ling SHIH ,  Chieh-Fei CHIU ,  Po-Wei LIU ,  Wen-Tuo HUANG ,  Yu-Ling HSU ,  Yong-Shiuan TSAIR

IPC: H01L27/11521 ,  H01L29/423 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/30625 ,  H01L21/3065 ,  H01L29/42344 ,  H01L29/78

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°