公开(公告)号：US20100112771A1

公开(公告)日：2010-05-06

申请号：US12654715

申请日：2009-12-30

申请人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon ,  Eun-ju Bae

发明人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon ,  Eun-ju Bae

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7839

摘要： Provided is a method of fabricating a Schottky barrier transistor. The method includes (a) forming a pair of cavities for forming a source forming portion and a drain forming portion having a predetermined depth and parallel to each other and a channel forming portion having a fin shape between the cavities in a substrate;(b) filling the pair of cavities with a metal; (c) forming a channel, a source, and a drain by patterning the channel forming portion, the source forming portion, and the drain forming portion in a direction perpendicular to a lengthwise direction of the channel forming portion; (d) sequentially forming a gate oxide layer and a gate metal layer that cover the channel, the source, and the drain on the substrate; and (e) forming a gate electrode corresponding to the channel by patterning the gate metal layer, wherein one of the operations (b) through (e) further comprises forming a Schottky barrier by annealing the substrate.

公开(公告)号：US20090162983A1

公开(公告)日：2009-06-25

申请号：US12149894

申请日：2008-05-09

申请人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon ,  Eun-ju Bae

发明人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon ,  Eun-ju Bae

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7839

摘要： Provided is a method of fabricating a Schottky barrier transistor. The method includes (a) forming a pair of cavities for forming a source forming portion and a drain forming portion having a predetermined depth and parallel to each other and a channel forming portion having a fin shape between the cavities in a substrate; (b) filling the pair of cavities with a metal; (c) forming a channel, a source, and a drain by patterning the channel forming portion, the source forming portion, and the drain forming portion in a direction perpendicular to a lengthwise direction of the channel forming portion; (d) sequentially forming a gate oxide layer and a gate metal layer that cover the channel, the source, and the drain on the substrate; and (e) forming a gate electrode corresponding to the channel by patterning the gate metal layer, wherein one of the operations (b) through (e) further comprises forming a Schottky barrier by annealing the substrate.

摘要翻译： 提供了制造肖特基势垒晶体管的方法。 该方法包括：（a）形成用于形成具有预定深度并彼此平行的源极形成部分和漏极形成部分的一对空腔，以及在衬底中的空腔之间具有翅片形状的沟道形成部分; （b）用金属填充一对空腔; （c）通过在垂直于沟道形成部分的长度方向的方向上图形化沟道形成部分，源形成部分和漏极形成部分来形成沟道，源极和漏极; （d）顺序地形成覆盖衬底上的沟道，源极和漏极的栅极氧化物层和栅极金属层; 以及（e）通过对所述栅极金属层进行构图来形成对应于所述沟道的栅电极，其中，所述（b）至（e）中的一个还包括通过使所述衬底退火来形成肖特基势垒。

公开(公告)号：US07674665B2

公开(公告)日：2010-03-09

申请号：US12149894

申请日：2008-05-09

申请人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon ,  Eun-ju Bae

发明人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon ,  Eun-ju Bae

IPC分类号： H01L21/338

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7839

摘要： Provided is a method of fabricating a Schottky barrier transistor. The method includes (a) forming a pair of cavities for forming a source forming portion and a drain forming portion having a predetermined depth and parallel to each other and a channel forming portion having a fin shape between the cavities in a substrate; (b) filling the pair of cavities with a metal; (c) forming a channel, a source, and a drain by patterning the channel forming portion, the source forming portion, and the drain forming portion in a direction perpendicular to a lengthwise direction of the channel forming portion; (d) sequentially forming a gate oxide layer and a gate metal layer that cover the channel, the source, and the drain on the substrate; and (e) forming a gate electrode corresponding to the channel by patterning the gate metal layer, wherein one of the operations (b) through (e) further comprises forming a Schottky barrier by annealing the substrate.

摘要翻译： 提供了制造肖特基势垒晶体管的方法。 该方法包括：（a）形成用于形成具有预定深度并彼此平行的源极形成部分和漏极形成部分的一对空腔，以及在衬底中的空腔之间具有翅片形状的沟道形成部分; （b）用金属填充一对空腔; （c）通过在垂直于沟道形成部分的长度方向的方向上图形化沟道形成部分，源形成部分和漏极形成部分来形成沟道，源极和漏极; （d）顺序地形成覆盖衬底上的沟道，源极和漏极的栅极氧化物层和栅极金属层; 以及（e）通过对所述栅极金属层进行构图来形成对应于所述沟道的栅电极，其中，所述（b）至（e）中的一个还包括通过使所述衬底退火来形成肖特基势垒。

公开(公告)号：US07902011B2

公开(公告)日：2011-03-08

申请号：US12654715

申请日：2009-12-30

申请人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon ,  Eun-ju Bae

发明人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon ,  Eun-ju Bae

IPC分类号： H01L21/338

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7839

摘要： Provided is a method of fabricating a Schottky barrier transistor. The method includes (a) forming a pair of cavities for forming a source forming portion and a drain forming portion having a predetermined depth and parallel to each other and a channel forming portion having a fin shape between the cavities in a substrate; (b) filling the pair of cavities with a metal; (c) forming a channel, a source, and a drain by patterning the channel forming portion, the source forming portion, and the drain forming portion in a direction perpendicular to a lengthwise direction of the channel forming portion; (d) sequentially forming a gate oxide layer and a gate metal layer that cover the channel, the source, and the drain on the substrate; and (e) forming a gate electrode corresponding to the channel by patterning the gate metal layer, wherein one of the operations (b) through (e) further comprises forming a Schottky barrier by annealing the substrate.

摘要翻译： 提供了制造肖特基势垒晶体管的方法。 该方法包括：（a）形成用于形成具有预定深度并彼此平行的源极形成部分和漏极形成部分的一对空腔，以及在衬底中的空腔之间具有翅片形状的沟道形成部分; （b）用金属填充一对空腔; （c）通过在垂直于沟道形成部分的长度方向的方向上图形化沟道形成部分，源形成部分和漏极形成部分来形成沟道，源极和漏极; （d）顺序地形成覆盖衬底上的沟道，源极和漏极的栅极氧化物层和栅极金属层; 以及（e）通过对所述栅极金属层进行构图来形成对应于所述沟道的栅电极，其中，所述（b）至（e）中的一个还包括通过使所述衬底退火来形成肖特基势垒。

公开(公告)号：US08115264B2

公开(公告)日：2012-02-14

申请号：US12007431

申请日：2008-01-10

申请人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon

发明人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon

IPC分类号： H01L29/78

CPC分类号： H01L21/823828 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： Provided is a semiconductor device that comprises a metal gate having a low sheet resistance characteristic and a high diffusion barrier characteristic and a method of fabricating the metal gate of the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, wherein the metal gate is formed of a metal nitride that contains Al or Si and includes upper and lower portions where the content of Al or Si is relatively high and a central portion where the content of Al or Si is relatively low.

摘要翻译： 提供一种半导体器件，其包括具有低薄层电阻特性和高扩散阻挡特性的金属栅极和制造半导体器件的金属栅极的方法。 半导体器件包括在栅极绝缘膜上形成的金属栅极，其中金属栅极由含有Al或Si的金属氮化物形成，并且包括Al或Si的含量相对较高的上部和下部以及中部， Al或Si的含量相对较低。

公开(公告)号：US20090065873A1

公开(公告)日：2009-03-12

申请号：US12007431

申请日：2008-01-10

申请人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon

发明人： Sung-ho Park ,  Jin-seo Noh ,  Joong S. Jeon

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823828 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： Provided is a semiconductor device that comprises a metal gate having a low sheet resistance characteristic and a high diffusion barrier characteristic and a method of fabricating the metal gate of the semiconductor device. The semiconductor device includes a metal gate formed on a gate insulating film, wherein the metal gate is formed of a metal nitride that contains Al or Si and includes upper and lower portions where the content of Al or Si is relatively high and a central portion where the content of Al or Si is relatively low.

摘要翻译： 提供一种半导体器件，其包括具有低薄层电阻特性和高扩散阻挡特性的金属栅极和制造半导体器件的金属栅极的方法。 半导体器件包括在栅极绝缘膜上形成的金属栅极，其中金属栅极由含有Al或Si的金属氮化物形成，并且包括Al或Si的含量相对较高的上部和下部以及中部， Al或Si的含量相对较低。

公开(公告)号：US08193030B2

公开(公告)日：2012-06-05

申请号：US12929122

申请日：2011-01-03

申请人： Chang-wook Moon ,  Joong S. Jeon ,  El Mostafa Bourim ,  Hyun-deok Yang

发明人： Chang-wook Moon ,  Joong S. Jeon ,  El Mostafa Bourim ,  Hyun-deok Yang

IPC分类号： H01L29/861

CPC分类号： H01L45/04 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675 ,  Y10S438/957 ,  Y10S438/958 ,  Y10S977/735 ,  Y10S977/742 ,  Y10S977/943

摘要： Nonvolatile memory devices may be fabricated to include a switching device on a substrate and/or a storage node electrically connected to the switching device. A storage node may include a lower metal layer electrically connected to the switching device, a first insulating layer, a middle metal layer, a second insulating layer, an upper metal layer, a carbon nanotube layer, and/or a passivation layer stacked on the lower metal layer.

摘要翻译： 可以制造非易失性存储器件，以在电连接到开关器件的衬底和/或存储节点上包括开关器件。 存储节点可以包括电连接到开关装置的下金属层，堆叠在开关装置上的第一绝缘层，中间金属层，第二绝缘层，上金属层，碳纳米管层和/或钝化层 下层金属层。

公开(公告)号：US20080164533A1

公开(公告)日：2008-07-10

申请号：US12000494

申请日：2007-12-13

申请人： Hyun-Deok Yang ,  Chang-wook Moon ,  Joong S. Jeon

发明人： Hyun-Deok Yang ,  Chang-wook Moon ,  Joong S. Jeon

IPC分类号： H01L29/49 ,  H01L21/44

CPC分类号： H01L29/0847 ,  H01L21/28518 ,  H01L29/66628 ,  H01L29/78

摘要： Example embodiments relate to a method of manufacturing a germanosilicide and a semiconductor device having the germanosilicide. A method according to example embodiments may include providing a substrate having at least a portion formed of silicon germanium. A metal layer may be formed on the silicon germanium. A thermal process may be performed on the substrate at a relatively high pressure to form the germanosilicide.

摘要翻译： 示例性实施方案涉及制造锗硅酸盐的方法和具有锗硅酸盐的半导体器件。 根据示例性实施例的方法可以包括提供具有由硅锗形成的至少一部分的衬底。 可以在硅锗上形成金属层。 可以在相对较高的压力下在基材上进行热处理以形成硅酸锗。

公开(公告)号：US07071051B1

公开(公告)日：2006-07-04

申请号：US10761009

申请日：2004-01-20

申请人： Joong S. Jeon ,  Robert B. Clark-Phelps ,  Qi Xiang ,  Huicai Zhong

发明人： Joong S. Jeon ,  Robert B. Clark-Phelps ,  Qi Xiang ,  Huicai Zhong

IPC分类号： H01L21/8238

CPC分类号： H01L21/28194 ,  H01L29/51 ,  H01L29/513 ,  H01L29/7833

摘要： According to one exemplary embodiment, a method for forming a field-effect transistor on a substrate comprises a step of forming a buffer layer on the substrate, where the buffer layer comprises ALD silicon dioxide. The buffer layer can be formed by utilizing a silicon tetrachloride precursor in an atomic layer deposition process, for example. The buffer layer comprises substantially no pin-hole defects and may have a thickness, for example, that is less than approximately 5.0 Angstroms. The method further comprises forming a high-k dielectric layer over the buffer layer. The high-k dielectric layer may be, for example, hafnium oxide, zirconium oxide, or aluminum oxide. According to this exemplary embodiment, the method further comprises forming a gate electrode layer over the high-k dielectric layer. The gate electrode layer may be polycrystalline silicon, for example.

摘要翻译： 根据一个示例性实施例，在衬底上形成场效应晶体管的方法包括在衬底上形成缓冲层的步骤，其中缓冲层包含ALD二氧化硅。 例如，可以在原子层沉积工艺中利用四氯化硅前体形成缓冲层。 缓冲层基本上不包括针孔缺陷，并且可以具有例如小于约5.0埃的厚度。 该方法还包括在缓冲层上形成高k电介质层。 高k电介质层可以是例如氧化铪，氧化锆或氧化铝。 根据该示例性实施例，该方法还包括在高k电介质层上形成栅电极层。 栅电极层例如可以是多晶硅。

公开(公告)号：US07026211B1

公开(公告)日：2006-04-11

申请号：US10795890

申请日：2004-03-08

申请人： Rinji Sugino ,  Joong S. Jeon ,  Robert B. Ogle, Jr.

发明人： Rinji Sugino ,  Joong S. Jeon ,  Robert B. Ogle, Jr.

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor component having smooth, void-free conductive layers and a method for manufacturing the semiconductor component. Surface features such as gate structures are formed on a semiconductor substrate. A layer of insulating material is formed on the gate structures and a layer of polysilicon is formed on the layer of insulating material. The layer of polysilicon is annealed in a hydrogen ambient to redistribute the silicon atoms of the polysilicon layer. Redistribution of the atoms fills voids that may be present in the layer of polysilicon and smoothes the surface of the layer of polysilicon. Another layer of polysilicon is formed over the annealed layer of polysilicon. This polysilicon layer is annealed in a hydrogen ambient to redistribute the silicon atoms and smooth the surface of the polysilicon layer, thereby forming a subsequently annealed polysilicon layer. Control gate structures are formed from the subsequently annealed polysilicon layer.

摘要翻译： 具有光滑无空隙的导电层的半导体部件和半导体部件的制造方法。 诸如栅极结构的表面特征形成在半导体衬底上。 在栅极结构上形成绝缘材料层，在绝缘材料层上形成多晶硅层。 多晶硅层在氢环境中退火以重新分布多晶硅层的硅原子。 原子的再分布填充可能存在于多晶硅层中的空隙，并且平滑多晶硅层的表面。 在多晶硅的退火层上形成另一层多晶硅。 该多晶硅层在氢环境中退火以重新分配硅原子并平滑多晶硅层的表面，从而形成随后退火的多晶硅层。 控制栅结构由随后退火的多晶硅层形成。