公开(公告)号：US08039247B2

公开(公告)日：2011-10-18

申请号：US10586331

申请日：2005-01-19

申请人： Shoji Takeuchi ,  Hiroaki Suzuki ,  Hiroyuki Noji

发明人： Shoji Takeuchi ,  Hiroaki Suzuki ,  Hiroyuki Noji

IPC分类号： C12M1/34 ,  G01N1/28

CPC分类号： B01L3/5088 ,  B01J2219/00317 ,  B01J2219/00585 ,  B01J2219/00599 ,  B01J2219/00653 ,  B01J2219/00725 ,  B01L3/5027 ,  B01L2300/0819 ,  B01L2400/0472

摘要： To provide a method of forming a planar lipid-bilayer membrane for membrane protein analysis, by which downsizing, simplifying, and multichanneling of a device therefore are achieved. A planar lipid-bilayer membrane 24 is formed by filling a microchannel 12 with a buffer solution 18, the microchannel 12 disposed under a horizontal partition wall 13 having an aperture 14; applying a small amount of a lipid solution 20 as a droplet on the aperture 14 filled with the buffer solution 18 to thereby form a thin layer 21 of the lipid solution in a chamber, the chamber 17 being formed at a position corresponding to the aperture 14 and provided with a liquid trap 15 inside the chamber; and applying a buffer solution 23 as a droplet to the chamber 17 from the upper side of the chamber.

摘要翻译： 提供一种形成用于膜蛋白分析的平面脂双层膜的方法，由此实现了装置的小型化，简化和多元化。 通过用缓冲溶液18填充微通道12形成平面脂双层膜24，微通道12设置在具有孔14的水平分隔壁13的下方; 在填充有缓冲溶液18的孔14上施加少量作为液滴的脂质溶液20，从而在腔室中形成脂质溶液的薄层21，室17形成在对应于孔14的位置 并在室内设置有液体捕集器15; 并且从室的上侧将作为液滴的缓冲溶液23施加到室17。

公开(公告)号：US5825712A

公开(公告)日：1998-10-20

申请号：US912755

申请日：1997-08-18

申请人： Tomoki Higashi ,  Hiroyuki Noji

发明人： Tomoki Higashi ,  Hiroyuki Noji

IPC分类号： G11C11/401 ,  G01R31/28 ,  G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012 ,  G11C11/401

摘要： The present invention intends to provide a semiconductor device integrated circuit having an additive circuit capable of the evaluation of the dynamic performance of a memory block in a mixed logic and memory IC or a high-speed logic block in a semiconductor device integrated circuit, directly from the outside of the device. In order to evaluate the dynamic performance of the memory block or the high-speed logic block by using a tester, the device is provided on the chip with bus lines which bypass the peripheral logic and are connected to the input terminals of the memory block or the high-speed logic block. In the device, the delay time difference between the bus lines are measured from the outside of the device, at first. By use of the measurement result, the timing error of inputting a plurality of test pulse signals used for the dynamic performance evaluation is compensated. A switching element is provided between the reference line and each of the bus lines. A delay time measuring signal is input to each of external I/O pads connected to the bus line through which the delay time of the signal passing is measured, and then the differences in the delay time of all the bus lines are obtained on the basis of the signal delay time produced between the reference line and the each of the line. By use of the difference in the delay time of the lines, the input timing error when the memory block is measured with the tester is compensated, thereby precise evaluation of the memory block or the high-speed logic block is obtained.

摘要翻译： 本发明旨在提供一种半导体器件集成电路，其具有能够直接从半导体器件集成电路中的混合逻辑和存储器IC或高速逻辑块中的存储器块的动态性能评估的加法电路 设备的外部。 为了通过使用测试仪来评估存储器块或高速逻辑块的动态性能，该器件在芯片上提供有旁路外围逻辑并连接到存储器块的输入端的总线，或者 高速逻辑块。 在设备中，首先从设备的外部测量总线之间的延迟时间差。 通过使用测量结果，补偿了用于动态性能评估的输入多个测试脉冲信号的定时误差。 在参考线和每条总线之间提供开关元件。 延迟时间测量信号被输入到连接到总线的每个外部I / O焊盘，测量信号通过的延迟时间，然后基于所有总线的延迟时间的差异获得 在参考线和每条线之间产生的信号延迟时间。 通过使用线路的延迟时间的差异，补偿了使用测试器测量存储器块时的输入定时误差，从而获得存储块或高速逻辑块的精确评估。

公开(公告)号：US09399788B2

公开(公告)日：2016-07-26

申请号：US14344475

申请日：2012-08-31

申请人： Yoshimi Matsumoto ,  Kohei Hayama ,  Shouichi Sakakihara ,  Kunihiko Nishino ,  Akihito Yamaguchi ,  Hiroyuki Noji ,  Ryota Iino

发明人： Yoshimi Matsumoto ,  Kohei Hayama ,  Shouichi Sakakihara ,  Kunihiko Nishino ,  Akihito Yamaguchi ,  Hiroyuki Noji ,  Ryota Iino

IPC分类号： C12Q1/18

CPC分类号： C12Q1/18

摘要： The present disclosure describes a method capable of easily and rapidly inspecting the susceptibility of bacteria or fungi to an antimicrobial drug. The inspection method of the present disclosure is a method for inspecting susceptibility of bacteria or fungi to an antimicrobial drug using a micro-device having flow channels, including: incubating a mixture of the antimicrobial drug and a suspension to be inspected in the flow channels of the micro-device; and detecting bacteria or fungi derived from the suspension to be inspected in an observation area of the flow channels of the micro-device. The detecting step can be performed by detecting an increase or decrease in the number of or a change in shape of bacteria or fungi derived from the suspension to be inspected in the observation area by a microscope or the like.

摘要翻译： 本公开描述了能够容易且快速地检查细菌或真菌对抗微生物药物的敏感性的方法。 本公开的检查方法是使用具有流动通道的微型装置检测细菌或真菌对抗微生物药物的敏感性的方法，包括：将抗微生物药物和待检查的悬浮液的混合物在流动通道 微器件; 以及在微型装置的流路的观察区域中检测来自要检查的悬浮液的细菌或真菌。 检测步骤可以通过用显微镜等检测在观察区域中待检查的悬浮液的细菌或真菌的数量的增加或变化的形状的增加或减少来进行。

公开(公告)号：US08524447B2

公开(公告)日：2013-09-03

申请号：US12594198

申请日：2008-03-25

申请人： Hiroyuki Noji ,  Hiromi Imamura ,  Ryota Iino ,  Yasuyuki Yamada

发明人： Hiroyuki Noji ,  Hiromi Imamura ,  Ryota Iino ,  Yasuyuki Yamada

IPC分类号： C12Q1/68 ,  C12Q1/02 ,  C12N9/00 ,  C12N15/63

CPC分类号： C07K14/00 ,  C07K14/32 ,  C07K2319/60 ,  C12N9/14 ,  G01N33/533 ,  G01N33/542 ,  G01N33/573 ,  G01N33/582 ,  G01N2333/914

摘要： The object of the present invention is to provide a substance, which is easy to handle and enables the measurement of ATP with a high sensitivity regardless of the concentration of protein, and further a measuring method of ATP using the substance. Such object is solved with a fluorescence labelled fusion protein obtained by attaching two types of fluorescent substances of potential donor and acceptor for fluorescence resonance energy transfer (FRET) respectively to a protein which can cause structural changes depending on ATP binding, namely ε protein, which is the subunit of ATP synthetase, and further solved by contacting the fluorescence labelled fusion protein with a subject substance and then measuring the fluorescence spectra.

摘要翻译： 本发明的目的是提供一种容易处理的物质，并且能够高灵敏度地测量ATP，而与蛋白质的浓度无关，并且还提供了使用该物质的ATP的测量方法。 通过将两种类型的荧光共振能量转移（FRET）的潜在供体荧光物质和受体的荧光物质分别连接到能够引起结构变化（依赖于ATP结合的蛋白质，即ε蛋白）而得到的荧光标记的融合蛋白来解决这个问题。 是ATP合成酶的亚基，进一步通过荧光标记的融合蛋白与目标物质接触，然后测量荧光光谱。

公开(公告)号：US20100233692A1

公开(公告)日：2010-09-16

申请号：US12594198

申请日：2008-03-25

申请人： Hiroyuki Noji ,  Hiromi Imamura ,  Ryota Iino ,  Yasuyuki Yamada

发明人： Hiroyuki Noji ,  Hiromi Imamura ,  Ryota Iino ,  Yasuyuki Yamada

IPC分类号： C12Q1/68 ,  C12Q1/02 ,  C12N9/00 ,  C12N15/63 ,  C07H21/04

CPC分类号： C07K14/00 ,  C07K14/32 ,  C07K2319/60 ,  C12N9/14 ,  G01N33/533 ,  G01N33/542 ,  G01N33/573 ,  G01N33/582 ,  G01N2333/914

摘要： The object of the present invention is to provide a substance, which is easy to handle and enables the measurement of ATP with a high sensitivity regardless of the concentration of protein, and further a measuring method of ATP using the substance. Such object is solved with a fluorescence labelled fusion protein obtained by attaching two types of fluorescent substances of potential donor and acceptor for fluorescence resonance energy transfer (FRET) respectively to a protein which can cause structural changes depending on ATP binding, namely ε protein, which is the subunit of ATP synthetase, and further solved by contacting the fluorescence labelled fusion protein with a subject substance and then measuring the fluorescence spectra.

摘要翻译： 本发明的目的是提供一种容易处理的物质，并且能够高灵敏度地测量ATP，而与蛋白质的浓度无关，并且还提供了使用该物质的ATP的测量方法。 通过将两种荧光共振能量转移（FRET）的潜在供体荧光物质和受体的荧光物质分别连接到能够引起结构上依赖于ATP结合的结构变化的蛋白质而获得的荧光标记的融合蛋白来解决这个问题。 蛋白质，其是ATP合成酶的亚基，并且通过将荧光标记的融合蛋白与受试物质接触，然后测量荧光光谱进一步解决。

公开(公告)号：US06430717B1

公开(公告)日：2002-08-06

申请号：US09609775

申请日：2000-07-03

申请人： Hiroyuki Noji

发明人： Hiroyuki Noji

IPC分类号： G11C2900

CPC分类号： G11C29/46 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5004

摘要： A semiconductor integrated circuit device, which has an internal circuit that operates during a normal operation on the basis of a reference signal and input signals supplied from the outside of the device. A detecting circuit detects the voltage level of the reference signal. When the detecting circuit has detected that the reference signal is at a predetermined voltage level that differs from a voltage level assumed during the normal operation, a transfer circuit transfers an internal signal in the internal circuit to the outside of the device, instead of the regular output signal of the internal circuit.

摘要翻译： 一种半导体集成电路器件，其具有根据参考信号在正常操作期间操作的内部电路和从该器件外部提供的输入信号。 检测电路检测参考信号的电压电平。 当检测电路检测到参考信号处于与正常操作期间假设的电压电平不同的预定电压电平时，传送电路将内部电路中的内部信号传送到设备的外部，而不是常规的 内部电路的输出信号。

公开(公告)号：US5265057A

公开(公告)日：1993-11-23

申请号：US813510

申请日：1991-12-26

申请人： Tohru Furuyama ,  Hiroyuki Noji

发明人： Tohru Furuyama ,  Hiroyuki Noji

IPC分类号： H01L21/66 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C29/50 ,  G11C11/401

摘要： There is provided a semiconductor memory including a plurality of word lines, a plurality of bit lines intersecting the word lines, and a memory cell array having memory cells arranged at respective intersections of the word lines and bit lines. Word line selecting circuits select the word lines in accordance with an address signal and word line driving circuits are connected to the word lines for driving selected word lines. Selective stress applying circuitry selectively applies stress, during a stress test, to word lines in one of a plurality of word line groups into which all word lines are classified. The selective stress applying circuits includes an arrangement of MOS transistors and pads for applying stress to a word line group during the stress test.

摘要翻译： 提供了包括多个字线，与字线相交的多个位线的半导体存储器，以及具有布置在字线和位线的各个交叉处的存储单元的存储单元阵列。 字线选择电路根据地址信号选择字线，并且字线驱动电路连接到用于驱动所选字线的字线。 选择应力施加电路在应力测试期间选择性地将应力施加到所有字线被分类到的多个字线组之一中的字线。 选择应力施加电路包括在压力测试期间向字线组施加应力的MOS晶体管和焊盘的布置。

公开(公告)号：US20130345088A1

公开(公告)日：2013-12-26

申请号：US14003509

申请日：2012-03-07

申请人： Hiroyuki Noji ,  Ryota Iino ,  Suguru Araki

发明人： Hiroyuki Noji ,  Ryota Iino ,  Suguru Araki

IPC分类号： G01N33/543

CPC分类号： G01N33/54386 ,  B01J2219/00317 ,  B01J2219/00466 ,  B01J2219/00619 ,  B01J2219/00621 ,  B01L3/502715 ,  B01L3/502761 ,  B01L3/50853 ,  B01L2200/0642 ,  B01L2200/0668 ,  B01L2200/12 ,  B01L2300/0627 ,  B01L2300/0819 ,  B01L2300/0829 ,  B01L2300/0858 ,  B01L2300/0877 ,  B01L2300/161 ,  B01L2300/165 ,  G01N21/6452 ,  G01N33/54306 ,  G01N33/54313

摘要： This invention provides a technique enabling to detect target molecules of low concentration with high sensitivity. This invention includes (i) a step of introducing a hydrophilic solvent (42) containing beads (40),(41′) into a space (30) between (a) a lower layer section (10) including a plurality of receptacles (13) each of which is capable of storing only one of the beads (41),(41′) and which are separated from each other by a side wall (12) having a hydrophobic upper surface and (b) an upper layer section (20) facing a surface of the lower layer section (10) on which surface the plurality of receptacles (13) are provided; and (ii) a step of introducing a hydrophobic solvent (43) into the space (30), the step (ii) being carried out after the step (i).

摘要翻译： 本发明提供能够以高灵敏度检测低浓度的目标分子的技术。 本发明包括（i）将含有珠（40），（41'）的亲水性溶剂（42）引入到（a）包括多个容器（13）的下层部分（10）之间的空间（30） ），其每一个仅能够容纳一个珠（41），（41'），并且通过具有疏水性上表面的侧壁（12）和（b）上层部分（20'）彼此分离 ）面向设置有多个插座（13）的表面的下层部分（10）的表面; 和（ii）将疏水性溶剂（43）引入空间（30）的步骤，步骤（ii）在步骤（i）之后进行。

公开(公告)号：US6138255A

公开(公告)日：2000-10-24

申请号：US296270

申请日：1999-04-22

申请人： Hiroyuki Noji

发明人： Hiroyuki Noji

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C29/02 ,  G11C29/14 ,  G11C29/46 ,  G11C29/50 ,  G11C29/00

CPC分类号： G11C29/46 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5004

摘要： A semiconductor integrated circuit device is disclosed, which has an internal circuit that operates during a normal operation on the basis of a reference signal and input signals supplied from the outside of the device. A detecting circuit detects the voltage level of the reference signal. When the detecting circuit has detected that the reference signal is at a predetermined voltage level that differs from a voltage level assumed during the normal operation, a transfer circuit transfers an internal signal in the internal circuit to the outside of the device, instead of the regular output signal of the internal circuit.

摘要翻译： 公开了一种半导体集成电路器件，其具有内部电路，其基于参考信号和从器件的外部提供的输入信号在正常操作期间操作。 检测电路检测参考信号的电压电平。 当检测电路检测到参考信号处于与正常操作期间假设的电压电平不同的预定电压电平时，传送电路将内部电路中的内部信号传送到设备的外部，而不是常规的 内部电路的输出信号。

公开(公告)号：US5410512A

公开(公告)日：1995-04-25

申请号：US64438

申请日：1993-05-21

申请人： Satoru Takase ,  Tohru Furuyama ,  Donald C. Stark ,  Natsuki Kushiyama ,  Kiyofumi Sakurai ,  Hiroyuki Noji ,  Shigeo Ohshima

发明人： Satoru Takase ,  Tohru Furuyama ,  Donald C. Stark ,  Natsuki Kushiyama ,  Kiyofumi Sakurai ,  Hiroyuki Noji ,  Shigeo Ohshima

IPC分类号： G11C11/401 ,  G06F12/02 ,  G11C7/00 ,  G11C7/10 ,  G11C11/407 ,  G11C11/41

CPC分类号： G11C7/1021

摘要： A semiconductor memory device includes a silicon chip and sub-arrays formed in the chip. In each of the sub-arrays, memory cells arranged in a matrix form, word lines provided for respective rows of each of the sub-arrays, and bit lines provided for respective columns of each of the sub-arrays are arranged. Further, in the chip, amplifier groups for amplifying data read out from the memory cells are arranged for the respective sub-arrays. Amplifiers connected to respective bit lines are provided in the amplifier groups and the amplifiers each have a function of continuously holding data read out from the memory cell.

摘要翻译： 半导体存储器件包括形成在芯片中的硅芯片和子阵列。 在每个子阵列中，布置成矩阵形式的存储器单元，为每个子阵列的各行提供的字线，以及为每个子阵列的各列提供的位线。 此外，在芯片中，放置用于放大从存储单元读出的数据的放大器组用于各个子阵列。 连接到相应位线的放大器设置在放大器组中，并且放大器各自具有连续保持从存储单元读出的数据的功能。