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公开(公告)号：US20150213757A1
公开(公告)日：2015-07-30
申请号：US14418911
申请日：2013-07-26
IPC分类号： G09G3/32
CPC分类号： G09G3/3233 , G09G3/3266 , G09G3/3291 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2310/027 , G09G2310/0286 , G09G2310/0291 , G09G2310/0294 , G09G2320/0233 , G09G2320/029 , G09G2320/0295 , G09G2320/043 , H01L27/3276
摘要： An organic EL display device includes a controller, a data driver, and a DRAM which provides a gain correction memory and a threshold voltage correction memory. The data driver sends, to the controller, first and second measurement data Im corresponding to the first and second measuring data voltages Vm, respectively. The controller compares ideal characteristic data IO(P) with the first and second measurement data Im, and updates threshold voltage correction data Vt and gain correction data B2R based on the comparison results. The controller corrects video data Vm based on the threshold voltage correction data Vt and the gain correction data B2R. Thereby, both threshold voltage compensation and gain compensation of a drive transistor are performed with respect to each pixel circuit, while display is performed.
摘要翻译： 有机EL显示装置包括控制器，数据驱动器和提供增益校正存储器和阈值电压校正存储器的DRAM。 数据驱动器分别向控制器发送对应于第一和第二测量数据电压Vm的第一和第二测量数据Im。 控制器将理想特性数据IO（P）与第一和第二测量数据Im进行比较，并且基于比较结果更新阈值电压校正数据Vt和增益校正数据B2R。 控制器基于阈值电压校正数据Vt和增益校正数据B2R校正视频数据Vm。 由此，在进行显示的同时，对各像素电路进行驱动晶体管的阈值电压补偿和增益补偿。
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公开(公告)号：US20150009111A1
公开(公告)日：2015-01-08
申请号：US14371194
申请日：2012-12-14
发明人： Yoshimitsu Yamauchi
CPC分类号： G09G3/3648 , G06F1/3265 , G09G3/2003 , G09G3/3233 , G09G3/3688 , G09G2300/0833 , G09G2300/0842 , G09G2300/0866 , G09G2300/0876 , G09G2310/0216 , G09G2310/0251 , G09G2310/0272 , G09G2320/0271 , G09G2320/066 , G09G2330/023 , H01L27/1225 , H01L27/1255
摘要： Provided are a pixel circuit and a display device which support multi-gradation display and can prevent display quality from deteriorating with low power consumption. A pixel circuit (3) includes a first switch circuit (22) provided between a pixel node Np of a display element unit (21) and a data signal line SL, and a memory circuit (23) which restores the pixel node to an initial voltage state, based on a hold voltage stored in a storage node Nm. The memory circuit (23) includes a transistor T1 having a gate electrode connected to the storage node Nm, and a source electrode connected to the pixel node Np; a second switch circuit (24) which controls a conducting state between a drain electrode of the transistor T1 and a voltage supply line VSL, in response to a signal level of a first control signal line SWL; a third switch circuit (25) which controls a conducting state between the drain electrode and the gate electrode of the transistor T1, in response to a signal level of a second control signal line CSL; and a capacitor element Cst provided between the storage node Nm and the voltage supply line VSL.
摘要翻译： 提供了一种支持多等级显示的像素电路和显示装置，并且能够以低功耗来防止显示质量劣化。 像素电路（3）包括设置在显示元件单元（21）的像素节点Np和数据信号线SL之间的第一开关电路（22）和存储电路（23），其将像素节点恢复到初始 电压状态，基于存储在存储节点Nm中的保持电压。 存储电路（23）包括具有连接到存储节点Nm的栅电极的晶体管T1和连接到像素节点Np的源电极; 响应于第一控制信号线SWL的信号电平，控制晶体管T1的漏电极和电源线VSL之间的导通状态的第二开关电路（24）; 响应于第二控制信号线CSL的信号电平，控制晶体管T1的漏电极和栅电极之间的导通状态的第三开关电路（25）; 以及设置在存储节点Nm与电压供给线VSL之间的电容器元件Cst。
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公开(公告)号：US20140361960A1
公开(公告)日：2014-12-11
申请号：US14366089
申请日：2012-12-06
发明人： Yoshimitsu Yamauchi
IPC分类号： G09G3/32
CPC分类号： G09G3/3233 , G09G2300/0413 , G09G2300/0819 , G09G2300/0842 , G09G2320/0233 , G09G2320/045 , H01L51/5218 , H01L51/5265 , H01L2251/558
摘要： A pixel circuit includes: a light emitting element; an n-channel drive transistor T1 that has a source connected with an anode of the light emitting element, a gate connected with a pixel node, and controls a light emission current flowing in the light emitting element in accordance with a light emission control voltage between the gate and the source; a transfer transistor T2 which is interposed between a data signal line and the pixel node, and has a gate connected with a scan signal line; a control transistor T3 which is interposed between the source and a drain of the drive transistor T1, has a gate connected with the scan signal line, and comes into an ON state simultaneously with the transfer transistor T2; and a capacitance element which is interposed between the gate and the source of the drive transistor T1, and holds the light emission control voltage.
摘要翻译： 像素电路包括：发光元件; 具有与发光元件的阳极连接的源极的n沟道驱动晶体管T1，与像素节点连接的栅极，并且根据发光元件之间的发光控制电压来控制发光电流 门和源; 传输晶体管T2介于数据信号线和像素节点之间，并具有与扫描信号线连接的栅极; 介于驱动晶体管T1的源极和漏极之间的控制晶体管T3具有与扫描信号线连接的栅极，并与转移晶体管T2同时变为导通状态; 以及插入驱动晶体管T1的栅极和源极之间的电容元件，并且保持发光控制电压。
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公开(公告)号：US09159738B2
公开(公告)日：2015-10-13
申请号：US14387908
申请日：2013-02-14
发明人： Yoshimitsu Yamauchi
IPC分类号： G11C11/24 , H01L27/115 , G11C11/403 , G11C11/4074 , G11C16/10 , H01L29/786 , H01L27/12 , G11C16/04
CPC分类号： H01L27/11526 , G11C11/403 , G11C11/4074 , G11C16/0408 , G11C16/0433 , G11C16/10 , H01L27/115 , H01L27/1156 , H01L27/1225 , H01L29/7869
摘要： Provided is a semiconductor memory device including an oxide semiconductor insulated gate FET and having a capability to implement advanced performance without being affected by a variation in threshold voltage. A memory cell MC includes a memory node Nm formed at a connection point of a gate of a first transistor element T1, a source of a second transistor element T2, and one end of a capacitive element Cm, and a control node Nc formed at a connection point of a drain of the first transistor element T1 and a drain of the second transistor element T2. Each memory cell MC arranged in the same column includes the control node Nc connected to a shared first control line CL extending in a column direction, the first transistor element T1 having a source connected to a shared data signal line DL extending in the column direction, the second transistor element T2 having a gate connected to an individual first selection line WL, and the capacitive element Cm having the other end connected to an individual second selection line GL, and a switching element SE having one end connected to the first control line CL, and the other end connected to a voltage supply line VL is provided with respect to each first control line CL.
摘要翻译： 提供了一种半导体存储器件，其包括氧化物半导体绝缘栅极FET，并且具有在不受阈值电压变化的影响的情况下实现高级性能的能力。 存储单元MC包括形成在第一晶体管元件T1的栅极，第二晶体管元件T2的源极和电容元件Cm的一端的连接点处的存储器节点Nm，以及形成在第一晶体管元件 第一晶体管元件T1的漏极和第二晶体管元件T2的漏极的连接点。 布置在同一列中的每个存储单元MC包括连接到沿列方向延伸的共享第一控制线CL的控制节点Nc，第一晶体管元件T1具有连接到沿列方向延伸的共享数据信号线DL的源极， 第二晶体管元件T2具有连接到单独的第一选择线WL的栅极，以及另一端连接到单独的第二选择线GL的电容元件Cm，以及一端连接到第一控制线CL的开关元件SE 并且相对于每个第一控制线CL设置连接到电压供应线VL的另一端。
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公开(公告)号：US09583057B2
公开(公告)日：2017-02-28
申请号：US14371194
申请日：2012-12-14
发明人： Yoshimitsu Yamauchi
CPC分类号： G09G3/3648 , G06F1/3265 , G09G3/2003 , G09G3/3233 , G09G3/3688 , G09G2300/0833 , G09G2300/0842 , G09G2300/0866 , G09G2300/0876 , G09G2310/0216 , G09G2310/0251 , G09G2310/0272 , G09G2320/0271 , G09G2320/066 , G09G2330/023 , H01L27/1225 , H01L27/1255
摘要： Provided are a pixel circuit and a display device which support multi-gradation display and can prevent display quality from deteriorating with low power consumption. A pixel circuit (3) includes a first switch circuit (22) provided between a pixel node Np of a display element unit (21) and a data signal line SL, and a memory circuit (23) which restores the pixel node to an initial voltage state, based on a hold voltage stored in a storage node Nm. The memory circuit (23) includes a transistor T1 having a gate electrode connected to the storage node Nm, and a source electrode connected to the pixel node Np; a second switch circuit (24) which controls a conducting state between a drain electrode of the transistor T1 and a voltage supply line VSL, in response to a signal level of a first control signal line SWL; a third switch circuit (25) which controls a conducting state between the drain electrode and the gate electrode of the transistor T1, in response to a signal level of a second control signal line CSL; and a capacitor element Cst provided between the storage node Nm and the voltage supply line VSL.
摘要翻译： 提供了一种支持多等级显示的像素电路和显示装置，并且能够以低功耗来防止显示质量劣化。 像素电路（3）包括设置在显示元件单元（21）的像素节点Np和数据信号线SL之间的第一开关电路（22）和存储电路（23），其将像素节点恢复到初始 电压状态，基于存储在存储节点Nm中的保持电压。 存储电路（23）包括具有连接到存储节点Nm的栅电极的晶体管T1和连接到像素节点Np的源电极; 响应于第一控制信号线SWL的信号电平，控制晶体管T1的漏电极和电源线VSL之间的导通状态的第二开关电路（24）; 响应于第二控制信号线CSL的信号电平，控制晶体管T1的漏电极和栅电极之间的导通状态的第三开关电路（25）; 以及设置在存储节点Nm与电压供给线VSL之间的电容器元件Cst。
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公开(公告)号：US09460660B2
公开(公告)日：2016-10-04
申请号：US14366089
申请日：2012-12-06
发明人： Yoshimitsu Yamauchi
IPC分类号： G09G3/3233 , G09G3/32 , H01L51/52
CPC分类号： G09G3/3233 , G09G2300/0413 , G09G2300/0819 , G09G2300/0842 , G09G2320/0233 , G09G2320/045 , H01L51/5218 , H01L51/5265 , H01L2251/558
摘要： A pixel circuit includes: a light emitting element; an n-channel drive transistor T1 that has a source connected with an anode of the light emitting element, a gate connected with a pixel node, and controls a light emission current flowing in the light emitting element in accordance with a light emission control voltage between the gate and the source; a transfer transistor T2 which is interposed between a data signal line and the pixel node, and has a gate connected with a scan signal line; a control transistor T3 which is interposed between the source and a drain of the drive transistor T1, has a gate connected with the scan signal line, and comes into an ON state simultaneously with the transfer transistor T2; and a capacitance element which is interposed between the gate and the source of the drive transistor T1, and holds the light emission control voltage.
摘要翻译： 像素电路包括：发光元件; 具有与发光元件的阳极连接的源极的n沟道驱动晶体管T1，与像素节点连接的栅极，并且根据发光元件之间的发光控制电压来控制发光电流 门和源; 传输晶体管T2介于数据信号线和像素节点之间，并具有与扫描信号线连接的栅极; 介于驱动晶体管T1的源极和漏极之间的控制晶体管T3具有与扫描信号线连接的栅极，并与转移晶体管T2同时变为导通状态; 以及插入驱动晶体管T1的栅极和源极之间的电容元件，并且保持发光控制电压。
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公开(公告)号：US09305492B2
公开(公告)日：2016-04-05
申请号：US14418911
申请日：2013-07-26
CPC分类号： G09G3/3233 , G09G3/3266 , G09G3/3291 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2310/027 , G09G2310/0286 , G09G2310/0291 , G09G2310/0294 , G09G2320/0233 , G09G2320/029 , G09G2320/0295 , G09G2320/043 , H01L27/3276
摘要： An organic EL display device includes a controller, a data driver, and a DRAM which provides a gain correction memory and a threshold voltage correction memory. The data driver sends, to the controller, first and second measurement data Im corresponding to the first and second measuring data voltages Vm, respectively. The controller compares ideal characteristic data IO(P) with the first and second measurement data Im, and updates threshold voltage correction data Vt and gain correction data B2R based on the comparison results. The controller corrects video data Vm based on the threshold voltage correction data Vt and the gain correction data B2R. Thereby, both threshold voltage compensation and gain compensation of a drive transistor are performed with respect to each pixel circuit, while display is performed.
摘要翻译： 有机EL显示装置包括控制器，数据驱动器和提供增益校正存储器和阈值电压校正存储器的DRAM。 数据驱动器分别向控制器发送对应于第一和第二测量数据电压Vm的第一和第二测量数据Im。 控制器将理想特征数据IO（P）与第一和第二测量数据Im进行比较，并且基于比较结果更新阈值电压校正数据Vt和增益校正数据B2R。 控制器基于阈值电压校正数据Vt和增益校正数据B2R校正视频数据Vm。 由此，在进行显示的同时，对各像素电路进行驱动晶体管的阈值电压补偿和增益补偿。
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公开(公告)号：US09214469B2
公开(公告)日：2015-12-15
申请号：US14371202
申请日：2012-12-28
发明人： Yoshimitsu Yamauchi
IPC分类号： G11C16/10 , H01L27/115 , G11C11/405 , G11C11/403 , G11C16/04 , H01L27/12
CPC分类号： H01L27/11517 , G11C11/403 , G11C11/405 , G11C16/0408 , G11C16/10 , H01L27/11521 , H01L27/1156 , H01L27/1225
摘要： Provided is a semiconductor memory circuit including an oxide semiconductor insulated gate FET enabling advanced performance without being affected by a variation in threshold voltage. A semiconductor memory circuit MC includes a first transistor element T1 composed of an insulated gate FET having a gate electrode connected to a memory node N1, a drain electrode connected to an intermediate node N2, and a source electrode connected to a data I/O terminal DIO; a second transistor element T2 composed of an oxide semiconductor insulated gate FET having a gate electrode connected to a first control terminal CIN1, a drain electrode connected to the intermediate node N2, and a source electrode connected to the memory node N1; a capacitive element C1 having one end connected to a first voltage terminal VIN1 and the other end connected to the memory node N1; and a switching element S1 for controlling a conducting state between a second control terminal CIN2 or a second voltage terminal VIN2 or the first voltage terminal VIN1, and the intermediate node N2, based on a voltage level of at least the second control terminal CIN2.
摘要翻译： 提供了一种半导体存储器电路，其包括具有高性能的氧化物半导体绝缘栅极FET，而不受阈值电压的变化的影响。 半导体存储器电路MC包括：第一晶体管元件T1，其由具有连接到存储节点N1的栅电极，连接到中间节点N2的漏电极和连接到数据I / O端子的源电极的绝缘栅FET构成; DIO; 由具有连接到第一控制端子CIN1的栅电极，连接到中间节点N2的漏电极和连接到存储节点N1的源电极的氧化物半导体绝缘栅FET构成的第二晶体管元件T2; 电容元件C1，其一端连接到第一电压端子VIN1，另一端连接到存储器节点N1; 以及用于基于至少第二控制端子CIN2的电压电平来控制第二控制端子CIN2或第二电压端子VIN2或第一电压端子VIN1与中间节点N2之间的导通状态的开关元件S1。
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公开(公告)号：US09208826B2
公开(公告)日：2015-12-08
申请号：US14388436
申请日：2013-02-27
发明人： Yoshimitsu Yamauchi
IPC分类号： G11C11/24 , G11C5/02 , G11C11/405 , H01L27/115 , G11C11/40 , H01L27/12
CPC分类号： G11C5/02 , G11C11/24 , G11C11/40 , G11C11/405 , G11C14/0009 , H01L27/115 , H01L27/1156 , H01L27/1225
摘要： Provided is a semiconductor storage device with which it is possible to write information to individual memory cells in which a storage node is configured with an oxide semiconductor insulated-gate FET source and a terminal of a capacitor element being connected. A storage node is configured by connecting a source of a first transistor to one terminal of a capacitor element. A drain of the first transistor and a source of a second transistor are connected to each other. A drain of the second transistor is a data input terminal. A first control terminal, which is formed by a gate of the first transistor being connected to another terminal of the capacitor element, is connected to a wordline, which extends in the row direction. A second control terminal, which is formed of a gate of the second transistor terminal, is connected to a write control line, which extends in the column direction. The storage node is connected to a gate of a third transistor, and a current flowing between a drain and a source of the third transistor is controlled according to a voltage level of the storage node.
摘要翻译： 提供了一种半导体存储装置，其可以向存储节点配置有氧化物半导体绝缘栅FET FET和连接的电容器元件的端子的各个存储单元写入信息。 通过将第一晶体管的源极连接到电容器元件的一个端子来配置存储节点。 第一晶体管的漏极和第二晶体管的源极彼此连接。 第二晶体管的漏极是数据输入端子。 由连接到电容器元件的另一个端子的第一晶体管的栅极形成的第一控制端子连接到沿行方向延伸的字线。 由第二晶体管端子的栅极形成的第二控制端子连接到在列方向上延伸的写入控制线。 存储节点连接到第三晶体管的栅极，并且根据存储节点的电压电平来控制在第三晶体管的漏极和源极之间流动的电流。
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公开(公告)号：US20150049535A1
公开(公告)日：2015-02-19
申请号：US14388436
申请日：2013-02-27
发明人： Yoshimitsu Yamauchi
CPC分类号： G11C5/02 , G11C11/24 , G11C11/40 , G11C11/405 , G11C14/0009 , H01L27/115 , H01L27/1156 , H01L27/1225
摘要： Provided is a semiconductor storage device with which it is possible to write information to individual memory cells in which a storage node is configured with an oxide semiconductor insulated-gate FET source and a terminal of a capacitor element being connected. A storage node is configured by connecting a source of a first transistor to one terminal of a capacitor element. A drain of the first transistor and a source of a second transistor are connected to each other. A drain of the second transistor is a data input terminal. A first control terminal, which is formed by a gate of the first transistor being connected to another terminal of the capacitor element, is connected to a wordline, which extends in the row direction. A second control terminal, which is formed of a gate of the second transistor terminal, is connected to a write control line, which extends in the column direction. The storage node is connected to a gate of a third transistor, and a current flowing between a drain and a source of the third transistor is controlled according to a voltage level of the storage node.
摘要翻译： 提供了一种半导体存储装置，其可以向存储节点配置有氧化物半导体绝缘栅FET FET和连接的电容器元件的端子的各个存储单元写入信息。 通过将第一晶体管的源极连接到电容器元件的一个端子来配置存储节点。 第一晶体管的漏极和第二晶体管的源极彼此连接。 第二晶体管的漏极是数据输入端子。 由连接到电容器元件的另一个端子的第一晶体管的栅极形成的第一控制端子连接到沿行方向延伸的字线。 由第二晶体管端子的栅极形成的第二控制端子连接到在列方向上延伸的写入控制线。 存储节点连接到第三晶体管的栅极，并且根据存储节点的电压电平来控制在第三晶体管的漏极和源极之间流动的电流。
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