公开(公告)号：US20130037893A1

公开(公告)日：2013-02-14

申请号：US13336050

申请日：2011-12-23

Applicant: Seung Hyun LEE

Inventor： Seung Hyun LEE

IPC: H01L29/82

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/5607 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device includes a first free layer having a magnetic direction that changes according to a direction and an amount of a first current, a first tunnel insulating layer arranged on the first free layer, a pinned layer, arranged on the first tunnel insulating layer, having a magnetic direction set to a first direction, a second tunnel insulating layer arranged on the pinned layer, and a second free layer, arranged on the second tunnel insulating layer, having a magnetic direction that changes according to a direction and an amount of a second current.

Abstract translation: 半导体器件包括：第一自由层，其具有根据第一电流的方向和量而变化的磁方向，布置在第一自由层上的第一隧道绝缘层，布置在第一隧道绝缘层上的钉扎层， 具有设置在第一方向的磁方向，布置在被钉扎层上的第二隧道绝缘层和布置在第二隧道绝缘层上的第二自由层，具有根据方向和量的变化的磁方向 第二电流。

公开(公告)号：US20130018567A1

公开(公告)日：2013-01-17

申请号：US13313073

申请日：2011-12-07

Applicant: Sang Woo LIM ,  Seung Hyun LEE ,  In Oh HWANG

Inventor： Sang Woo LIM ,  Seung Hyun LEE ,  In Oh HWANG

IPC: F02D28/00

CPC classification number: B60W50/085 ,  B60W2050/0064 ,  B60W2540/28 ,  B60W2550/20 ,  B60W2550/40 ,  B60W2550/402 ,  F02D41/021 ,  F02D41/266 ,  F02D2200/60 ,  F02D2200/70 ,  F02D2200/701 ,  F02D2200/702

Abstract: A mobile terminal to control an Electronic Control Unit (ECU) of a vehicle includes a communication unit, a storage unit, and an ECU control unit. The communication unit communicates with the ECU, and the storage unit stores information collected from the ECU and status information collected inside or outside the mobile terminal. The ECU control unit determines a driving environment of the vehicle according to the status information collected, processes the information collected from the ECU, and controls the ECU. A method for controlling a vehicle ECU from a mobile terminal includes determining a driving environment, and remotely controlling the ECU from the mobile terminal based on the driving environment.

Abstract translation: 用于控制车辆的电子控制单元（ECU）的移动终端包括通信单元，存储单元和ECU控制单元。 通信单元与ECU通信，并且存储单元存储从ECU收集的信息和在移动终端内部或外部收集的状态信息。 ECU控制单元根据收集到的状态信息来确定车辆的行驶环境，处理从ECU收集的信息，并控制ECU。 一种用于从移动终端控制车辆ECU的方法包括：根据驾驶环境确定驾驶环境，并从移动终端远程控制ECU。

公开(公告)号：US20100224920A1

公开(公告)日：2010-09-09

申请号：US12643011

申请日：2009-12-21

Applicant: Seung Hyun LEE

Inventor： Seung Hyun LEE

IPC: H01L29/82 ,  H01L21/00

CPC classification number: H01L27/228 ,  G11C11/16

Abstract: A magnetoresistive memory cell includes a magnetic tunnel junction element; and a selection transistor, wherein the selection transistor includes a first conductive type semiconductor layer, a gate electrode formed on the first conductive type semiconductor layer with a gate insulation film interposed between the first conductive type semiconductor layer and the gate electrode, and second conductive type first and second diffusion regions formed in the first conductive type semiconductor such that the first and second diffusion regions are spaced apart from each other. The magnetic tunnel junction element includes a free magnetization layer, a fixed magnetization layer, and a tunnel barrier layer interposed between the free magnetization layer and the fixed magnetization layer, and the free magnetization layer of the magnetic tunnel junction element is electrically connected to any one of the first and second diffusion regions of the selection transistor.

Abstract translation: 磁阻存储单元包括磁性隧道结元件; 以及选择晶体管，其中所述选择晶体管包括第一导电类型半导体层，形成在所述第一导电类型半导体层上的栅电极，其中介于所述第一导电类型半导体层和所述栅极之间的栅极绝缘膜，以及第二导电类型 形成在第一导电型半导体中的第一和第二扩散区域使得第一和第二扩散区域彼此间隔开。 磁性隧道结元件包括自由磁化层，固定磁化层和介于自由磁化层和固定磁化层之间的隧道势垒层，并且磁性隧道结元件的自由磁化层电连接到任何一个 的选择晶体管的第一和第二扩散区域。

公开(公告)号：US20090121326A1

公开(公告)日：2009-05-14

申请号：US11953967

申请日：2007-12-11

Applicant: Jong Hoon KIM ,  Min Suk SUH ,  Seong Cheol KIM ,  Seung Taek YANG ,  Seung Hyun LEE

Inventor： Jong Hoon KIM ,  Min Suk SUH ,  Seong Cheol KIM ,  Seung Taek YANG ,  Seung Hyun LEE

IPC: H01L23/495 ,  H01L23/538

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H05K1/021 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0061 ,  H05K2201/10371 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/1572

Abstract: A semiconductor package module includes a circuit board including a board body having a receiving portion and conductive patterns formed on the board body; a semiconductor package received in the receiving portion and having conductive terminals electrically connected to the conductive patterns and an s semiconductor chip electrically connected to the conductive terminals; and a connection member electrically connecting the conductive patterns and the conductive terminals. In the present invention, after a receiving portion having a receiving space is formed in the board body of a circuit board and a semiconductor package is received in the receiving portion, and a connection terminal of the semiconductor package and a conductive pattern of the board body are electrically connected using a connection member, a plurality of semiconductor packages can be stacked in a single circuit board without increasing the thickness thereby significantly improving data storage capacity and data processing speed of the semiconductor package module.

Abstract translation: 一种半导体封装模块，包括：电路板，包括具有接收部分的基板主体和形成在所述基板主体上的导电图案; 接收在所述接收部分中并且具有电连接到所述导电图案的导电端子和与所述导电端子电连接的半导体芯片的半导体封装; 以及电连接导电图案和导电端子的连接构件。 在本发明中，在电路基板的基板主体中形成具有接收空间的接收部分，并且在接收部分中接收半导体封装的接收部分，以及半导体封装的连接端子和板体的导电图案 使用连接构件电连接，多个半导体封装可以堆叠在单个电路板中而不增加厚度，从而显着提高半导体封装模块的数据存储容量和数据处理速度。

公开(公告)号：US20120087171A1

公开(公告)日：2012-04-12

申请号：US12899912

申请日：2010-10-07

Applicant: Seung Hyun LEE

Inventor： Seung Hyun LEE

IPC: G11C11/00 ,  H01L21/02

CPC classification number: H01L27/2463 ,  H01L27/222 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233

Abstract: A semiconductor memory device with a variable resistance element includes a plurality of active areas isolated from one another by an isolation layer formed in a substrate, a plurality of word lines crossing over the plurality of active areas, an auxiliary source line disposed between two selected word lines and commonly connected to at least two active areas among the plurality of active areas between the two selected word lines, and a plurality of contact plugs each connected to a corresponding active area.

Abstract translation: 具有可变电阻元件的半导体存储器件包括通过形成在衬底中的隔离层彼此隔离的多个有源区域，跨越多个有源区域的多个字线，设置在两个选择字之间的辅助源极线 并且通常连接到两个所选字线之间的多个有效区域中的至少两个有效区域，以及各自连接到相应的有效区域的多个接触插塞。

公开(公告)号：US20110287584A1

公开(公告)日：2011-11-24

申请号：US13197249

申请日：2011-08-03

Applicant: Min Suk SUH ,  Seung Taek YANG ,  Seung Hyun LEE ,  Jong Hoon KIM

Inventor： Min Suk SUH ,  Seung Taek YANG ,  Seung Hyun LEE ,  Jong Hoon KIM

IPC: H01L21/78

CPC classification number: H01L23/4334 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/19 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/15311

Abstract: A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.

Abstract translation: 半导体封装包括具有上表面的半导体芯片，与上表面连接的侧表面，以及形成在上表面上的焊盘。 形成第一绝缘层图案以覆盖半导体芯片的上表面和侧表面并且暴露接合焊盘。 再分配线路放置在第一绝缘层图案上，并且包括第一再分配线部分和第二再分配线部分。 第一再分配线部分具有与接合焊盘连接的端部并且对应于半导体芯片的上表面，并且第二再分配线部分从第一再分配线部分延伸超过半导体芯片的侧表面 。 在半导体芯片上形成第二绝缘层图案，并且暴露出第一再分配线部分和第二再分配线部分的部分。

公开(公告)号：US20110233795A1

公开(公告)日：2011-09-29

申请号：US13158813

申请日：2011-06-13

Applicant: Jong Hoon KIM ,  Min Suk SUH ,  Seung Taek YANG ,  Seung Hyun LEE ,  Tae Min KANG

Inventor： Jong Hoon KIM ,  Min Suk SUH ,  Seung Taek YANG ,  Seung Hyun LEE ,  Tae Min KANG

IPC: H01L23/488

CPC classification number: H01L25/0652 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06562 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/83005

Abstract: A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

Abstract translation: 堆叠的晶片级封装包括具有第一焊盘的第一半导体芯片和具有第二焊盘的第二半导体芯片。 半导体芯片的两个接合焊盘面向相同的方向。 第二半导体芯片与第一半导体芯片平行设置。 第三半导体芯片设置在用作支撑衬底的第一和第二半导体芯片上。 第三半导体芯片具有在附接时在第一和第二半导体芯片之间露出的第三焊盘。 最后，再分布结构电连接到第一，第二和第三键合焊盘。

公开(公告)号：US20090230565A1

公开(公告)日：2009-09-17

申请号：US12244322

申请日：2008-10-02

Applicant: Seung Taek YANG ,  Min Suk SUH ,  Seung Hyun LEE ,  Jong Hoon KIM

Inventor： Seung Taek YANG ,  Min Suk SUH ,  Seung Hyun LEE ,  Jong Hoon KIM

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/481 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05099

Abstract: A stacked semiconductor package and a method for manufacturing the same are presented which exhibit a reduced electrical resistance and an increased junction force. The semiconductor package includes at least two semiconductor chips stacked upon each other. Each semiconductor chip has a plurality of bonding pads formed on upper surfaces and has via-holes. First wiring lines are located on the upper surfaces of the semiconductor chips, on the surfaces of the via-holes, and respectively connected onto their respective bonding pads. Second wiring lines are located on lower surfaces of the semiconductor chips and on the surfaces of the respective via-holes which connect to their respective first wiring lines. The semiconductor chips are stacked so that the first wiring lines on an upper surface of an upwardly positioned semiconductor chip are respectively joined with corresponding second wiring lines formed on a lower surface of a downwardly positioned semiconductor chip.

Abstract translation: 本发明提供一种叠层半导体封装及其制造方法，其具有降低的电阻和增加的接合力。 半导体封装包括彼此堆叠的至少两个半导体芯片。 每个半导体芯片具有形成在上表面上并具有通孔的多个接合焊盘。 第一布线位于半导体芯片的上表面上，位于通孔的表面上，分别连接到它们各自的焊盘上。 第二布线位于半导体芯片的下表面和连接到它们各自的第一布线的相应通孔的表面上。 半导体芯片被堆叠，使得位于向上定位的半导体芯片的上表面上的第一布线分别与形成在向下定位的半导体芯片的下表面上的对应的第二布线接合。

公开(公告)号：US20180001137A1

公开(公告)日：2018-01-04

申请号：US15640536

申请日：2017-07-01

Applicant: Seung Hyun LEE

Inventor： Seung Hyun LEE

IPC: A63B23/04 ,  A63B21/04 ,  A63B23/035 ,  A63B21/00 ,  A63B23/00

CPC classification number: A63B23/0488 ,  A63B21/00069 ,  A63B21/0442 ,  A63B21/0552 ,  A63B21/4015 ,  A63B21/4034 ,  A63B21/4043 ,  A63B23/03516 ,  A63B2023/006 ,  A63B2071/024 ,  A63B2210/50 ,  A63B2225/09

Abstract: A leg stretching apparatus can be safely used without a risk of damage, with a simple coupling and can be conveniently installed at a site at which leg stretching is desired to enable efficient leg stretching. The leg stretching apparatus includes a fixing plate in which a first fixing plate, which includes a plurality of coupling grooves, and a second fixing plate, which includes a plurality of coupling protrusions corresponding to the coupling grooves, are detachably configured. A fixing part has one end coupled to the first fixing plate and another end equipped with an adjusting part. An elastic string has one end fixed to the fixing part and another end extending in a longitudinal direction of the fixing part, and opposingly branched with two free end portions behind the first fixing plate. A moving part is installed at the second fixing plate to guide the branching of the elastic string.

公开(公告)号：US20130039121A1

公开(公告)日：2013-02-14

申请号：US13336102

申请日：2011-12-23

Applicant: Seung Hyun LEE

Inventor： Seung Hyun LEE

IPC: G11C11/16 ,  H01L29/82

CPC classification number: G11C11/161 ,  G11C11/5607 ,  H01L27/228 ,  H01L43/08

Abstract: A magneto-resistance memory device includes a first pinned layer having a first magnetic polarity regardless of current applied to the first pinned layer, a first tunnel insulating layer arranged on the first pinned layer, a first free layer arranged on the first tunnel insulating layer and having a magnetic polarity that changes in response to current of a first amount, a second pinned layer coupled to the first free layer and having the first magnetic polarity regardless of current applied to the first pinned layer, a second tunnel insulating layer arranged on the second pinned layer, a second free layer arranged on the second tunnel insulating layer and having a magnetic polarity that changes in response to current of a second amount, wherein the second amount is smaller than the first amount, and a connection layer.

Abstract translation: 磁阻存储器件包括具有第一磁极性的第一被钉扎层，而不管施加到第一被钉扎层的电流如何，布置在第一钉扎层上的第一隧道绝缘层，布置在第一隧道绝缘层上的第一自由层和 具有响应于第一量的电流而变化的磁极性，耦合到第一自由层并且具有第一磁极性的第二被钉扎层，而不管施加到第一被钉扎层的电流如何;第二隧道绝缘层，布置在第二自由层上 所述第二自由层布置在所述第二隧道绝缘层上，并且具有响应于第二量的电流而变化的磁极性，其中所述第二量小于所述第一量，以及连接层。