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    ADAPTIVE NEGATIVE WORD LINE VOLTAGE
    1.
    发明公开
    ADAPTIVE NEGATIVE WORD LINE VOLTAGE 审中-公开

    公开(公告)号：US20240071527A1

    公开(公告)日：2024-02-29

    申请号：US17896330

    申请日：2022-08-26

    Applicant: SanDisk Technologies LLC

    Inventor： Xiaoyu Che ,  Yanjie Wang ,  Runchen Fang

    IPC: G11C16/34 ,  G11C16/08

    CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/3495

    Abstract: A storage device comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines. A controller, coupled to the non-volatile memory, configured to: determine, based on a stage of a product lifetime of the non-volatile memory, a negative word line setting for implementing during performance of a first operation; perform the first operation, the first operation including adjusting, based on the negative word line setting, a negative word line relative parameter; determine, based on another stage of the product lifetime of the non-volatile memory, another negative word line setting for implementing during performance of a second operation; and perform the second operation, the second operation including adjusting, based on the other negative word line setting, another negative word line relative parameter.

    POWER SAVING AND FAST READ SEQUENCE FOR NON-VOLATILE MEMORY
    4.
    发明申请
    POWER SAVING AND FAST READ SEQUENCE FOR NON-VOLATILE MEMORY 有权

    公开(公告)号：US20220208276A1

    公开(公告)日：2022-06-30

    申请号：US17135071

    申请日：2020-12-28

    Applicant: SanDisk Technologies LLC

    Inventor： Jianzhi Wu ,  Jia Li ,  Yanjie Wang

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56

    Abstract: A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.

    NAND STRING READ VOLTAGE ADJUSTMENT
    5.
    发明公开
    NAND STRING READ VOLTAGE ADJUSTMENT 审中-公开

    公开(公告)号：US20240086074A1

    公开(公告)日：2024-03-14

    申请号：US17940465

    申请日：2022-09-08

    Applicant: SanDisk Technologies LLC

    Inventor： Yi Song ,  Jiahui Yuan ,  Yanjie Wang

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

    Abstract: An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block. The control circuit is further configured to adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block. The first and second predetermined amounts are based on respective locations of the first and second regions in the block.

    DYNAMIC WORD LINE BOOSTING DURING PROGRAMMING OF A MEMORY DEVICE
    6.
    发明公开
    DYNAMIC WORD LINE BOOSTING DURING PROGRAMMING OF A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240079063A1

    公开(公告)日：2024-03-07

    申请号：US17939160

    申请日：2022-09-07

    Applicant: SanDisk Technologies LLC

    Inventor： Han-Ping Chen ,  Yanjie Wang

    IPC: G11C16/10 ,  G11C16/04

    CPC classification number: G11C16/10 ,  G11C16/0483

    Abstract: The memory device includes a memory block, which includes a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry in communication with the memory block. The control circuitry is configured to perform a programming operation to program the memory cells of a selected word line of the plurality of word lines. During the programming operation, the control circuitry is configured to apply a programming pulse VPGM to a selected word line to the selected word line, apply a first pass voltage to a first set of word lines of the plurality of word lines, the first set of word lines being adjacent the selected word line, and apply a second pass voltage to a second set of word lines of the plurality of word. The first pass voltage is greater than the second pass voltage.

    FOGGY-FINE DRAIN-SIDE SELECT GATE RE-PROGRAM FOR ON-PITCH SEMI-CIRCLE DRAIN SIDE SELECT GATES
    7.
    发明公开
    FOGGY-FINE DRAIN-SIDE SELECT GATE RE-PROGRAM FOR ON-PITCH SEMI-CIRCLE DRAIN SIDE SELECT GATES 审中-公开

    公开(公告)号：US20240079061A1

    公开(公告)日：2024-03-07

    申请号：US17901197

    申请日：2022-09-01

    Applicant: SanDisk Technologies LLC

    Inventor： Xiaoyu Che ,  Yanjie Wang

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/16

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/16

    Abstract: A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. A control means is configured to program drain-side select gate transistors of the memory holes to an initial transistor threshold voltage using pulses increasing in magnitude by a first transistor step amount during each of a plurality of foggy loops of a foggy program operation. The control means is also configured to program the drain-side select gate transistors of the memory holes to a target transistor threshold voltage using pulses increasing in magnitude by a second transistor step amount during each of a plurality of fine loops of a fine program operation. The first transistor step amount is greater than the second transistor step amount.

    PEAK CURRENT AND PROGRAM TIME OPTIMIZATION THROUGH LOOP DEPENDENT VOLTAGE RAMP TARGET AND TIMING CONTROL
    9.
    发明申请
    PEAK CURRENT AND PROGRAM TIME OPTIMIZATION THROUGH LOOP DEPENDENT VOLTAGE RAMP TARGET AND TIMING CONTROL 有权

    公开(公告)号：US20220284964A1

    公开(公告)日：2022-09-08

    申请号：US17191153

    申请日：2021-03-03

    Applicant: SanDisk Technologies LLC

    Inventor： Yanjie Wang ,  Henry Chin ,  Guirong Liang ,  Jianzhi Wu

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a predicted parasitic capacitance associated with the programming state of the control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.

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