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公开(公告)号：US11721397B2
公开(公告)日：2023-08-08
申请号：US17135071
申请日：2020-12-28
Applicant: SanDisk Technologies LLC
Inventor： Jianzhi Wu , Jia Li , Yanjie Wang
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C11/5671
Abstract: A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.
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公开(公告)号：US10910060B1
公开(公告)日：2021-02-02
申请号：US16568986
申请日：2019-09-12
Applicant: SanDisk Technologies LLC
Inventor： Jianzhi Wu , Xiang Yang
Abstract: An apparatus comprising strings of non-volatile memory cells is disclosed. Each string comprises non-volatile memory cells, an operative select gate, and a dummy select gate. The apparatus comprises a select line connected to the operative select gate of each string, and a dummy line connected to the dummy select gate of each string. The dummy line is an immediate neighbor to the select line. The apparatus comprises a control circuit configured to apply a voltage waveform to the select line while the dummy line is floating. The control circuit is configured to detect a floating voltage on the dummy line while applying the voltage waveform to the select line. The control circuit is configured to determine a condition of the voltage waveform at a target location on the select line based on the floating voltage on the dummy line.
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公开(公告)号：US11636897B2
公开(公告)日：2023-04-25
申请号：US17191153
申请日：2021-03-03
Applicant: SanDisk Technologies LLC
Inventor： Yanjie Wang , Henry Chin , Guirong Liang , Jianzhi Wu
Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a predicted parasitic capacitance associated with the programming state of the control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.
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公开(公告)号：US10978160B2
公开(公告)日：2021-04-13
申请号：US16236792
申请日：2018-12-31
Applicant: SanDisk Technologies LLC
Inventor： Jianzhi Wu , Xiang Yang , Jun Wan
Abstract: Example techniques that mitigate against memory hole shorts during an erase operation for memory cells in a string include an example method in which, during an erase operation, erase pulses are applied to the word lines of the memory string and terminated at different times based. In some instances, the erase pulses applied to the word lines of the memory string are terminated based on the temperature of the memory cells of the memory string. In further implementations, the erase pulses applied to the word lines of the memory string are boosted for different times depending on the location of the word line along the memory string during the erase operation.
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公开(公告)号：US20220208276A1
公开(公告)日：2022-06-30
申请号：US17135071
申请日：2020-12-28
Applicant: SanDisk Technologies LLC
Inventor： Jianzhi Wu , Jia Li , Yanjie Wang
Abstract: A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.
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Patent Agency Ranking
公开(公告)号：US10741257B1
公开(公告)日：2020-08-11
申请号：US16453291
申请日：2019-06-26
Applicant: SanDisk Technologies LLC
Inventor： Jianzhi Wu , Xiang Yang
Abstract: A method and system are provided for reading a non-transitory memory array. When a default read operation is performed and has failed, a dynamic sensing bit line voltage (VBLC) enhanced read or a dynamic sense time read is performed. According to the dynamic VBLC enhanced read or the dynamic sense time enhanced read, the VBLC or the sense time is increased, and a read is performed with the increased VBLC or increased sense time. If this enhanced read is unsuccessful, and if a maximum VBLC or a maximum sense time has not yet been reached, the VBLC or the sense time is increased again, and another read is performed. Once the maximum VBLC or a maximum sense time has been reached, if the read is still not successful, a read failure is reported.
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公开(公告)号：US10535412B2
公开(公告)日：2020-01-14
申请号：US15963647
申请日：2018-04-26
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Huai-Yuan Tseng , Deepanshu Dutta , Jianzhi Wu , Gerrit Jan Hemink
Abstract: A memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.
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公开(公告)号：US20220284964A1
公开(公告)日：2022-09-08
申请号：US17191153
申请日：2021-03-03
Applicant: SanDisk Technologies LLC
Inventor： Yanjie Wang , Henry Chin , Guirong Liang , Jianzhi Wu
Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a predicted parasitic capacitance associated with the programming state of the control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.
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9.发明授权公开(公告)号：US11250926B2
公开(公告)日：2022-02-15
申请号：US16654696
申请日：2019-10-16
Applicant: SanDisk Technologies LLC
Inventor： Jianzhi Wu , Xiang Yang
IPC: G11C29/38 , G11C16/26 , G11C16/04 , G11C16/08 , G11C16/24 , G11C29/52 , G11C11/56 , G11C16/10 , G06F11/10
Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes memory cells arranged in sectors. Each of the memory cells includes a control gate in communication with one of a plurality of word lines and a drain coupled to one of a plurality of bit lines and is configured to retain a threshold voltage. A control circuit is in communication with the memory cells and is configured to read the threshold voltage of each of the memory cells using default read parameters. The control circuit determines whether reading the non-volatile memory cells using the default read parameters is successful. The control circuit dynamically tests and adjusts read parameters based on whether reading the memory cells using the read parameters is successful in response to determining that reading the memory cells using the default read parameters is not successful.
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10.发明申请公开(公告)号：US20210118518A1
公开(公告)日：2021-04-22
申请号：US16654696
申请日：2019-10-16
Applicant: SanDisk Technologies LLC
Inventor： Jianzhi Wu , Xiang Yang
IPC: G11C29/38 , G11C16/26 , G11C16/04 , G11C16/08 , G11C16/24 , G11C11/56 , G11C16/10 , G06F11/10 , G11C29/52
Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes memory cells arranged in sectors. Each of the memory cells includes a control gate in communication with one of a plurality of word lines and a drain coupled to one of a plurality of bit lines and is configured to retain a threshold voltage. A control circuit is in communication with the memory cells and is configured to read the threshold voltage of each of the memory cells using default read parameters. The control circuit determines whether reading the non-volatile memory cells using the default read parameters is successful. The control circuit dynamically tests and adjusts read parameters based on whether reading the memory cells using the read parameters is successful in response to determining that reading the memory cells using the default read parameters is not successful.
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