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1.发明授权Non-volatile memory with multi-word line select for defect detection operations 有权具有多字线选择的非易失性存储器用于缺陷检测操作公开(公告)号：US09449694B2
公开(公告)日：2016-09-20
申请号：US14477339
申请日：2014-09-04
发明人： Rajan Paudel , Jagdish Sabde , Sagar Magia , Khanh Nguyen
CPC分类号： G11C16/10 , G11C8/14 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C29/26 , G11C2029/1202 , G11C2029/2602
摘要： A stress mode for use in testing non-volatile memory arrays for a number of types of defects is described. More specifically, a multi-word line select option for a given block can be used for a group of selected word lines to be set to the a programming or other high voltage, while the unselected word lines of the block are set to a pass voltage to minimize electric field differences in order to avoid disturb. For example, a group of selected word lines could number 4, 8 or 16. The multi-word line option can be applied to one block per plane, so that if there are two memory planes, for example, two such blocks can be selected simultaneously for the multi-word line option for those blocks.
摘要翻译： 描述了用于测试用于多种类型的缺陷的非易失性存储器阵列的应力模式。 更具体地，对于给定块的多字线选择选项可以用于要设置为编程或其它高电压的一组选定字线，而块的未选字线被设置为通过电压 以尽量减少电场差异，以避免干扰。 例如，一组选定的字线可以编号为4,8或16.多字线选项可以应用于每个平面的一个块，使得如果存在两个存储器平面，则可以选择两个这样的块 同时为这些块的多字行选项。
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2.发明授权Techniques for detection and treating memory hole to local interconnect marginality defects 有权用于检测和处理存储器孔到局部互连边缘缺陷的技术公开(公告)号：US09224502B1
公开(公告)日：2015-12-29
申请号：US14596751
申请日：2015-01-14
发明人： Jagdish Sabde , Sagar Magia , Jayavel Pachamuthu , Deepak Raghu
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483 , G11C29/025 , G11C29/06 , G11C29/12005 , G11C29/50008
摘要： Techniques are presented for the determination and handling of defects in non-volatile arrays, particularly those having a 3D or BiCS type of arrangement where NAND strings run in a vertical direction relative to the substrate. In such an arrangement, the NAND strings are formed along memory holes and connected to global bit lines, and are separated into blocks or sub-blocks by vertical local interconnects, such as for source lines, and connected to a corresponding global line. To determine defects, an AC stress can be applied between the interconnects and the bit lines/NAND strings, after which a defect determination operation can be performed. This technique can also be implemented at the system level by having the controller instruct the memory to perform it as part of an adaptive defect determination operation.
摘要翻译： 提出了用于确定和处理非挥发性阵列中的缺陷的技术，特别是具有相对于衬底的垂直方向上的NAND串的3D或BiCS类型的布置。 在这种布置中，NAND串沿着存储器孔形成并连接到全局位线，并且通过垂直局部互连（例如用于源极线）分离成块或子块，并连接到相应的全局线。 为了确定缺陷，可以在互连和位线/ NAND串之间施加AC应力，之后可以执行缺陷确定操作。 通过使控制器指示存储器作为自适应缺陷确定操作的一部分来执行该技术，也可以在系统级实现该技术。
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公开(公告)号：US09530514B1
公开(公告)日：2016-12-27
申请号：US15005487
申请日：2016-01-25
发明人： Jagdish Sabde , Jayavel Pachamuthu , Sagar Magia
CPC分类号： G11C29/04 , G11C16/0483 , G11C16/3436 , G11C29/024 , G11C2029/5002
摘要： Detecting defects in select gates of memory cell strings is disclosed. An electrical short between adjacent select gates may be detected. The select gate may comprises a transistor having an adjustable threshold voltage. An operation configured to change a threshold voltage of one select transistor and to maintain a threshold voltage of an adjacent select transistor may be performed. The select transistors may be flagged in response to the threshold voltage of either select transistor failing to meet a target threshold voltage in response to the operation. The operation may be an erase operation or a program operation.
摘要翻译： 公开了检测存储器单元串的选择栅极中的缺陷。 可以检测相邻选择门之间的电短路。 选择栅极可以包括具有可调阈值电压的晶体管。 可以执行配置为改变一个选择晶体管的阈值电压并维持相邻选择晶体管的阈值电压的操作。 可以响应于选择晶体管的阈值电压响应于该操作而不能满足目标阈值电压而标记选择晶体管。 该操作可以是擦除操作或程序操作。
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4.发明申请Non-Volatile Memory with Multi-Word Line Select for Defect Detection Operations 有权具有多字线选择的非易失性存储器用于缺陷检测操作公开(公告)号：US20160071594A1
公开(公告)日：2016-03-10
申请号：US14477339
申请日：2014-09-04
发明人： Rajan Paudel , Jagdish Sabde , Sagar Magia , Khanh Nguyen
CPC分类号： G11C16/10 , G11C8/14 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C29/26 , G11C2029/1202 , G11C2029/2602
摘要： A stress mode for use in testing non-volatile memory arrays for a number of types of defects is described. More specifically, a multi-word line select option for a given block can be used for a group of selected word lines to be set to the a programming or other high voltage, while the unselected word lines of the block are set to a pass voltage to minimize electric field differences in order to avoid disturb. For example, a group of selected word lines could number 4, 8 or 16. The multi-word line option can be applied to one block per plane, so that if there are two memory planes, for example, two such blocks can be selected simultaneously for the multi-word line option for those blocks.
摘要翻译： 描述了用于测试用于多种类型的缺陷的非易失性存储器阵列的应力模式。 更具体地，对于给定块的多字线选择选项可以用于要设置为编程或其它高电压的一组选定字线，而块的未选字线被设置为通过电压 以尽量减少电场差异，以避免干扰。 例如，一组选定的字线可以编号为4,8或16.多字线选项可以应用于每个平面的一个块，使得如果存在两个存储器平面，则可以选择两个这样的块 同时为这些块的多字行选项。
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公开(公告)号：US09269446B1
公开(公告)日：2016-02-23
申请号：US14681653
申请日：2015-04-08
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3459 , G11C2216/14 , H01L27/11582
摘要： For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program. These techniques are particularly applicable to memory devices have a 3D structure, such as of BiCS type, where the slow programming can arise from defects of the spacing between the memory holes, in which the NAND strings are formed, and the local interconnects, such as for connecting common source lines and which run in a vertical direction between groups of NAND strings. The slow to program NAND strings can be recorded and this information can be used when writing data to the NAND strings. Several methods of writing data along a word line that includes such slow to program cells are described.
摘要翻译： 对于具有NAND型架构的非易失性存储器件，呈现用于确定编程缓慢的NAND串的技术。 这些技术特别适用于具有诸如BiCS类型的3D结构的存储器件，其中慢速编程可能由存在于其中形成NAND串的存储器孔之间的间隔的缺陷和局部互连（例如 用于连接公共源极线并且在NAND串的组之间沿垂直方向运行。 可以记录NAND串的编程速度慢，并且可以在将数据写入NAND串时使用该信息。 描述了沿着包括这种慢速编程单元的字线写入数据的几种方法。
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公开(公告)号：US09240249B1
公开(公告)日：2016-01-19
申请号：US14475138
申请日：2014-09-02
发明人： Jagdish Sabde , Sagar Magia , Jayavel Pachamuthu
CPC分类号： G11C29/025 , G11C16/0483 , G11C29/06 , G11C29/12005 , G11C2029/1204
摘要： A number of techniques for determining bit line related defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Defects related to bit line to NAND string contacts are determined by application of an AC stress mode along bit lines, followed by a defect detection operation. If the AC stress is applied to be out of phase on adjacent bit lines, this can also be used to accelerate bit line to bit line defects. The subsequent defect determination phase can include an erase operation followed a read to determine whether the NAND strings of the erased block read as erased, a process that can also be followed by a program and subsequent read to further check for defects.
摘要翻译： 提出了用于确定非易失性存储器阵列中的位线相关缺陷的许多技术，其特别适用于诸如BiCS类型的3D NAND存储器。 通过沿着位线施加AC应力模式来确定与NAND串触点的位线有关的缺陷，随后进行缺陷检测操作。 如果交流应力施加在相邻位线上的相位异相，也可以用来加速位线到位线的缺陷。 随后的缺陷确定阶段可以包括读取之后的擦除操作，以确定被擦除的块的NAND串是否被读取，还可以跟随程序和随后的读取以进一步检查缺陷。
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公开(公告)号：US09830998B2
公开(公告)日：2017-11-28
申请号：US14716794
申请日：2015-05-19
IPC分类号： G11C29/10 , G11C29/06 , G11C29/02 , G11C5/02 , G11C16/34 , G11C29/50 , G11C16/04 , H01L27/11582
CPC分类号： G11C29/025 , G11C5/025 , G11C16/0483 , G11C16/349 , G11C16/3495 , G11C29/06 , G11C29/10 , G11C29/50008 , H01L27/11582
摘要： A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns. The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation.
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公开(公告)号：US20160260495A1
公开(公告)日：2016-09-08
申请号：US14919472
申请日：2015-10-21
发明人： Rajan Paudel , Jagdish Sabde , Mrinal Kochar , Sagar Magia
CPC分类号： G11C16/3427 , G11C16/16 , G11C16/26 , G11C16/3431 , G11C16/3445 , G11C29/025 , G11C29/44 , G11C29/50 , G11C2029/1202
摘要： Techniques are provided for operating a memory device which detect word line short circuits, such as short circuits between adjacent word lines. In an example implementation, during a programming operation, the number of program loops used to complete programming or reach another programming milestone for WLn are counted. If the number of program loops exceeds a loop count limit, the memory cells of WLn+1 are evaluated to determine whether a short circuit is present. The evaluation involves a read operation which counts erased state memory cells in the upper tail of the Vth distribution of WLn+1. If the count exceeds a bit count limit, it is concluded that a short circuit exits between WLn and WLn+1, and a corrective action is taken. The loop count limit is adjusted lower as the number of program-erase cycles increases.
摘要翻译： 提供了用于操作检测字线短路（例如相邻字线之间的短路）的存储器件的技术。 在示例实现中，在编程操作期间，计数用于完成编程或到达WLn的另一编程里程碑的程序循环的数量。 如果程序循环数超过循环计数限制，则评估WLn + 1的存储单元以确定是否存在短路。 评估涉及对WLn + 1的Vth分布的上尾部中的擦除状态存储单元进行计数的读取操作。 如果计数超过位计数限制，则可以断定WLn和WLn + 1之间出现短路，并采取纠正措施。 循环计数限制随着编程擦除周期数的增加而调低。
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公开(公告)号：US20160012914A1
公开(公告)日：2016-01-14
申请号：US14328027
申请日：2014-07-10
发明人： Sagar Magia , Jagdish Sabde
CPC分类号： G11C11/5628 , G11C16/0483 , G11C29/025 , G11C29/06 , G11C2029/1202
摘要： A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.
摘要翻译： 提出了用于确定非易失性存储器阵列中的缺陷的许多技术，其特别适用于诸如BiCS类型的3D NAND存储器。 通过应用AC应力模式，随后进行缺陷检测操作来确定存储器块内的字线到字短路。 可以使用块间应力和检测操作来确定不同块之间的字线到字线泄漏。 选择栅极泄漏线泄漏，字线和其他选择线都是考虑的，也是字线的短路，并选择线到本地源极线。 除了字线和选择线缺陷之外，还提供了用于确定位线和低电压电路之间的短路的技术，如在读出放大器中。
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公开(公告)号：US20160012904A1
公开(公告)日：2016-01-14
申请号：US14328070
申请日：2014-07-10
发明人： Jagdish Sabde , Sagar Magia , Khanh Nguyen
IPC分类号： G11C16/34
CPC分类号： G11C16/3422 , G11C16/0466 , G11C16/0483 , G11C16/16 , G11C29/025 , G11C29/06 , G11C2029/1202 , H01L27/1157 , H01L27/11582
摘要： A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.
摘要翻译： 提出了用于确定非易失性存储器阵列中的缺陷的许多技术，其特别适用于诸如BiCS类型的3D NAND存储器。 通过应用AC应力模式，随后进行缺陷检测操作来确定存储器块内的字线到字短路。 可以使用块间应力和检测操作来确定不同块之间的字线到字线泄漏。 选择栅极泄漏线泄漏，字线和其他选择线都是考虑的，也是字线的短路，并选择线到本地源极线。 除了字线和选择线缺陷之外，还提供了用于确定位线和低电压电路之间的短路的技术，如在读出放大器中。
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