公开(公告)号：US20170323850A1

公开(公告)日：2017-11-09

申请号：US15659125

申请日：2017-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGHO RHA ,  JONGMIN BAEK ,  WOOKYUNG YOU ,  SANGHOON AHN ,  NAEIN LEE

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/764

CPC classification number: H01L23/5226 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.

公开(公告)号：US20180083099A1

公开(公告)日：2018-03-22

申请号：US15628675

申请日：2017-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGMIN BAEK ,  VIETHA NGUYEN ,  WOOKYUNG YOU ,  Sangshin JANG ,  BYUNGHEE KIM ,  Kyu-Hee HAN

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  H01L21/768

Abstract: A semiconductor device comprises a lower structure on a substrate and including a recess region, first and second barrier layers covering an inner surface of the recess region and a top surface of the lower structure, the inner surface of the recess region including a bottom surface and an inner sidewall connecting the bottom surface to the top surface of the lower structure, and an interlayer dielectric layer provided on the second barrier layer and defining an air gap in the recess region. A first step coverage is obtained by dividing a thickness of the first barrier layer on an inner sidewall of the recess region by a thickness of the first barrier layer on the top surface of the lower structure. A second step coverage is obtained by dividing a thickness of the second barrier layer on the inner sidewall of the recess region by a thickness of the second barrier layer on the top surface of the lower structure. The first step coverage is different from the second step coverage.

公开(公告)号：US20170278797A1

公开(公告)日：2017-09-28

申请号：US15618811

申请日：2017-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGHO RHA ,  JONGMIN BAEK ,  WOOKYUNG YOU ,  SANGHOON AHN ,  NAE-IN LEE

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/02 ,  H01L21/321 ,  H01L21/288 ,  H01L21/306 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/02178 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

公开(公告)号：US20160247759A1

公开(公告)日：2016-08-25

申请号：US15146112

申请日：2016-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHO RHA ,  JONGMIN BAEK ,  WOOKYUNG YOU ,  SANGHOON AHN ,  NAEIN LEE

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.

公开(公告)号：US20150332955A1

公开(公告)日：2015-11-19

申请号：US14606970

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOKYUNG YOU ,  JONGMIN BAEK ,  SANGHOON AHN ,  SANGHO RHA ,  NAEIN LEE

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

Abstract translation: 本公开描述了半导体器件及其制造方法。 该方法包括在衬底上形成层间绝缘层，并在层间绝缘层中形成导电图案。 层间绝缘层的上部的孔密度高于层间绝缘层的下部的孔密度，层间绝缘层的中间部分的孔密度朝向层间绝缘层的上部逐渐增加 。 在导电图案之间设置气隙。

公开(公告)号：US20240096797A1

公开(公告)日：2024-03-21

申请号：US18330672

申请日：2023-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINJAE KANG ,  YEONGGIL KIM ,  WOOKYUNG YOU ,  WOOJIN LEE ,  JAYEONG HEO

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53295 ,  H01L27/088

Abstract: Disclosed is a semiconductor device including a substrate, conductive structures on the substrate and extending in parallel to each other in a first direction, and a first interlayer dielectric layer in first and second trenches between the conductive structures. A width in a second direction of the first trench may be less than a width in the second direction of the second trench. The first interlayer dielectric layer may include a lower interlayer dielectric layer and an upper interlayer dielectric layer on the lower interlayer dielectric layer, sequentially stacked. A mechanical strength of the upper interlayer dielectric layer may be greater than a mechanical strength of the lower interlayer dielectric layer.

公开(公告)号：US20170076975A1

公开(公告)日：2017-03-16

申请号：US15359724

申请日：2016-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOKYUNG YOU ,  JONGMIN BAEK ,  SANGHOON AHN ,  SANGHO RHA ,  NAEIN LEE

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

Abstract translation: 本公开描述了半导体器件及其制造方法。 该方法包括在衬底上形成层间绝缘层，并在层间绝缘层中形成导电图案。 层间绝缘层的上部的孔密度高于层间绝缘层的下部的孔密度，层间绝缘层的中间部分的孔密度朝向层间绝缘层的上部逐渐增加 。 在导电图案之间设置气隙。

公开(公告)号：US20160322254A1

公开(公告)日：2016-11-03

申请号：US15205168

申请日：2016-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOKYUNG YOU ,  Sanghoon Ahn ,  Sangho Rha ,  Jongmin Baek ,  Nae-In Lee

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76837 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance.