-
公开(公告)号：US11848307B2
公开(公告)日：2023-12-19
申请号：US17478247
申请日：2021-09-17
发明人： Sungwoo Park , Ungcheon Kim , Heonwoo Kim , Yunseok Choi
IPC分类号： H01L23/48 , H01L25/065 , H01L23/498 , H01L23/367 , H01L23/31 , H01L23/00
CPC分类号： H01L25/0655 , H01L23/3121 , H01L23/367 , H01L23/481 , H01L23/49811 , H01L23/49833 , H01L23/562
摘要： A semiconductor package includes a base substrate and an interposer substrate. The interposer substrate includes a semiconductor substrate, a first passivation layer, a wiring region, a through via penetrating through the semiconductor substrate and the first passivation layer, and a second passivation layer covering at least a portion of the first passivation layer and having an opening exposing a lower surface of the through via. The semiconductor package further includes a conductive pillar extending from the opening of the second passivation layer; and a conductive bump disposed between the conductive pillar and the base substrate. The opening of the second passivation layer has inclined side surfaces such that a width of the opening decreases towards the first passivation layer, and side surfaces of the conductive pillar are positioned to overlap the inclined side surfaces of the second passivation layer in a vertical direction.
-
公开(公告)号：US20210026249A1
公开(公告)日：2021-01-28
申请号：US16593149
申请日：2019-10-04
发明人： Byunghoon Lee , Changyoung Jeong , Byunggook Kim , Maenghyo Cho , Muyoung Kim , Junghwan Moon , Sungwoo Park , Hyungwoo Lee , Joonmyung Choi
IPC分类号： G03F7/20 , G05B19/4097 , H01L21/027
摘要： There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.
-
公开(公告)号：US20230352386A1
公开(公告)日：2023-11-02
申请号：US18347519
申请日：2023-07-05
发明人： Ungcheon Kim , Sungwoo Park , Yukyung Park , Seungkwan Ryu
IPC分类号： H01L23/498 , H01L21/48
CPC分类号： H01L23/49822 , H01L23/49838 , H01L21/4857 , H01L23/49816 , H01L25/18
摘要： An interposer including a base layer, a redistribution structure on a first surface of the base layer and including a conductive redistribution pattern, a first lower protection layer on a second surface of the base layer, a lower conductive pad on the first lower protection layer, a through electrode connecting the conductive redistribution pattern and the lower conductive pad, a second lower protection layer on the first lower protection layer, including a different material than the first lower protection layer, and contacting at least a portion of the lower conductive pad, and an indentation formed in an outer edge region of the interposer to provide a continuous angled sidewall extending entirely through the second lower protection layer and through at least a portion of the first protection layer.
-
4.发明申请公开(公告)号：US20230052195A1
公开(公告)日：2023-02-16
申请号：US17971321
申请日：2022-10-21
发明人： Yukyung Park , Ungcheon Kim , Sungwoo Park , Seungkwan Ryu
IPC分类号： H01L23/498 , H01L25/18 , H01L21/48 , H01L23/538
摘要： Provided is an interposer for a semiconductor package, the interposer including an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface, a first through-electrode structure and a second through-electrode structure each passing through the interposer substrate and protruding from the first main surface, a connection terminal structure contacting both the first through-electrode structure and the second through-electrode structure, and a photosensitive polymer layer arranged between the connection terminal structure and the interposer substrate, and between the first through-electrode structure and the second through-electrode structure.
-
5.发明申请公开(公告)号：US20210175161A1
公开(公告)日：2021-06-10
申请号：US17038306
申请日：2020-09-30
发明人： Yukyung Park , Ungcheon Kim , Sungwoo Park , Seungkwan Ryu
IPC分类号： H01L23/498 , H01L25/18 , H01L21/48 , H01L23/538
摘要： Provided is an interposer for a semiconductor package, the interposer including an interposer substrate comprising a first main surface and a second main surface opposite to the first main surface, a first through-electrode structure and a second through-electrode structure each passing through the interposer substrate and protruding from the first main surface, a connection terminal structure contacting both the first through-electrode structure and the second through-electrode structure, and a photosensitive polymer layer arranged between the connection terminal structure and the interposer substrate, and between the first through-electrode structure and the second through-electrode structure.
-
公开(公告)号：US12119288B2
公开(公告)日：2024-10-15
申请号：US17658614
申请日：2022-04-08
发明人： Youngbae Kim , Sungwoo Park
IPC分类号： H01L23/495 , H01L23/00 , H01L23/31
CPC分类号： H01L23/4951 , H01L23/49548 , H01L24/16 , H01L23/3107 , H01L23/49513 , H01L24/14 , H01L2224/1415 , H01L2224/16258
摘要： A semiconductor package includes: a lead frame that includes a first surface and a second surface opposite to the first surface, where the lead frame includes a first lead that extends in a first direction, and a plurality of second leads that are spaced apart from the first lead on both sides of the first lead; at least one semiconductor chip mounted on the first surface of the lead frame by a plurality of bumps; and an encapsulant that encapsulates the lead frame and the at least one semiconductor chip, wherein the first lead has a groove in the first surface that partitions the plurality of bumps in contact with the first lead.
-
公开(公告)号：US12080691B2
公开(公告)日：2024-09-03
申请号：US17585122
申请日：2022-01-26
发明人： Sungwoo Park , Heonwoo Kim , Sangcheon Park , Wonil Lee
IPC分类号： H01L25/10 , H01L23/00 , H01L23/538 , H01L25/065
CPC分类号： H01L25/105 , H01L23/5384 , H01L23/5386 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06544 , H01L2924/37001
摘要： A semiconductor device including an interposer including a central region and an edge region entirely surrounding the central region, wherein the interposer includes a wiring structure disposed in the first region and a metal structure disposed continuously within the entirety of the second region, a first semiconductor chip mounted in the central region and connected to the wiring structure, and a second semiconductor chip mounted in the central region adjacent to the first semiconductor chip and connected to the second wiring structure.
-
8.发明授权Package for semiconductor device including guide rings and manufacturing method of the same 有权包括引导环的半导体器件的封装及其制造方法公开(公告)号：US09018041B2
公开(公告)日：2015-04-28
申请号：US14064467
申请日：2013-10-28
发明人： Han-shin Youn , Yonghwan Kwon , YoungHoon Ro , Woojae Kim , Sungwoo Park
CPC分类号： H01L24/03 , H01L21/563 , H01L23/49816 , H01L23/49838 , H01L24/16 , H01L24/48 , H01L25/105 , H01L25/16 , H01L2224/0401 , H01L2224/16225 , H01L2224/16235 , H01L2224/16237 , H01L2224/32225 , H01L2224/48227 , H01L2224/50 , H01L2224/73204 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2225/1082 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad. At least one electrode is coupled between the first pad and the second pad. The semiconductor package includes a guide ring formed at a periphery of the electrode between the first substrate and the second substrate.
摘要翻译： 示例性实施例涉及半导体封装。 半导体封装包括第一衬底，其包括第一焊盘，与第一衬底向上间隔开的第二衬底，并且包括与第一焊盘相对的第二焊盘。 至少一个电极耦合在第一焊盘和第二焊盘之间。 半导体封装包括形成在第一基板和第二基板之间的电极的周边处的引导环。
-
公开(公告)号：US12072637B2
公开(公告)日：2024-08-27
申请号：US17971297
申请日：2022-10-21
发明人： Byunghoon Lee , Changyoung Jeong , Byunggook Kim , Maenghyo Cho , Muyoung Kim , Junghwan Moon , Sungwoo Park , Hyungwoo Lee , Joonmyung Choi
IPC分类号： G03F7/00 , G05B19/4097 , H01L21/027
CPC分类号： G03F7/705 , G05B19/4097 , H01L21/0273 , G05B2219/45028
摘要： There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.
-
公开(公告)号：US20230047588A1
公开(公告)日：2023-02-16
申请号：US17971297
申请日：2022-10-21
发明人： Byunghoon Lee , Changyoung Jeong , Byunggook Kim , Maenghyo Cho , Muyoung Kim , Junghwan Moon , Sungwoo Park , Hyungwoo Lee , Joonmyung Choi
IPC分类号： G03F7/20 , H01L21/027 , G05B19/4097
摘要： There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.
-
-
-
-
-
-
-
-
-
搜索结果
17 条记录 (耗时 0.021 秒)
