公开(公告)号：US11662665B2

公开(公告)日：2023-05-30

申请号：US17672937

申请日：2022-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Maenghyo Cho ,  Changyoung Jeong ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee

IPC: G03F7/20 ,  H01L21/027 ,  G03F7/40 ,  G05B19/4099 ,  G06F30/25

CPC classification number: G03F7/705 ,  G03F7/40 ,  G03F7/70033 ,  G03F7/70608 ,  G05B19/4099 ,  G06F30/25 ,  H01L21/0274 ,  G05B2219/45031

Abstract: A lithography method using a multiscale simulation includes estimating a shape of a virtual resist pattern for a selected resist based on a multiscale simulation; forming a test resist pattern by performing an exposure process on a layer formed of the selected resist; determining whether an error range between the test resist pattern and the virtual resist pattern is in an allowable range; and forming a resist pattern on a patterning object using the selected resist when the error range is in the allowable range. The multiscale simulation may use molecular scale simulation, quantum scale simulation, and a continuum scale simulation, and may model a unit lattice cell of the resist by mixing polymer chains, a photo-acid generator (PAG), and a quencher.

公开(公告)号：US20210026249A1

公开(公告)日：2021-01-28

申请号：US16593149

申请日：2019-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/20 ,  G05B19/4097 ,  H01L21/027

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

公开(公告)号：US12072637B2

公开(公告)日：2024-08-27

申请号：US17971297

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/00 ,  G05B19/4097 ,  H01L21/027

CPC classification number: G03F7/705 ,  G05B19/4097 ,  H01L21/0273 ,  G05B2219/45028

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

公开(公告)号：US20230047588A1

公开(公告)日：2023-02-16

申请号：US17971297

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/20 ,  H01L21/027 ,  G05B19/4097

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

公开(公告)号：US11493850B2

公开(公告)日：2022-11-08

申请号：US16593149

申请日：2019-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byunghoon Lee ,  Changyoung Jeong ,  Byunggook Kim ,  Maenghyo Cho ,  Muyoung Kim ,  Junghwan Moon ,  Sungwoo Park ,  Hyungwoo Lee ,  Joonmyung Choi

IPC: G03F7/20 ,  H01L21/027 ,  G05B19/4097

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.