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    Semiconductor devices
    2.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11380711B2

    公开(公告)日：2022-07-05

    申请号：US17154583

    申请日：2021-01-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sohyeon Lee ,  Sungsu Moon ,  Jaeduk Lee ,  Ikhyung Joo

    IPC: H01L27/12 ,  H01L21/84 ,  H01L29/08 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

    Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.

    SEMICONDUCTOR DEVICES
    3.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250024677A1

    公开(公告)日：2025-01-16

    申请号：US18660638

    申请日：2024-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kang Lib Kim ,  Sungsu Moon ,  Seahoon Lee ,  Junhee Lim

    IPC: H10B43/27 ,  H10B43/35 ,  H10B43/40

    Abstract: A semiconductor device includes a gate electrode structure, a memory channel structure, and first and second contact plugs. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction, and each of the gate electrodes extends in a second direction. The gate electrode structure has a staircase shape including step layers each of which includes two gate electrodes. The memory channel structure extends through the gate electrode structure. The first contact plug contacts an upper surface of a first gate electrode of the two gate electrodes at an upper level in a corresponding step layer. The second contact plug contacts a sidewall of a second gate electrode of the two gate electrodes at a lower level in the corresponding step layer. The second contact plug extends in the first direction and is electrically insulated from gate electrodes disposed below the second gate electrode.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE, AN ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME
    4.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE, AN ELECTRONIC SYSTEM INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20240373632A1

    公开(公告)日：2024-11-07

    申请号：US18406913

    申请日：2024-01-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kang Lib Kim ,  Sungsu Moon ,  Sea Hoon Lee ,  Junhee Lim

    IPC: H10B43/27 ,  H01L23/522 ,  H10B43/40

    Abstract: Disclosed are 3D semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a first substrate including a cell array region and a contact region, a stack structure including interlayers and gate electrodes and including a pad part having a stepwise structure on the contact region, a first dielectric layer covering the pad part of the stack structure, a second dielectric layer on the first dielectric layer, an interlayer capacitor between the first dielectric layer and the second dielectric layer, cell contact plugs penetrating the pad part of the stack structure, the first dielectric layer, and the second dielectric layer and correspondingly connected to the gate electrodes, and lower and upper conductive lines penetrating the pad part of the stack structure, the first dielectric layer, and the second dielectric layer and electrically connected to the interlayer capacitor.

    Semiconductor devices with enhanced substrate isolation
    5.
    发明授权
    Semiconductor devices with enhanced substrate isolation 有权

    公开(公告)号：US12080799B2

    公开(公告)日：2024-09-03

    申请号：US17715887

    申请日：2022-04-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sohyeon Lee ,  Sungsu Moon ,  Jaeduk Lee ,  Ikhyung Joo

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/786

    CPC classification number: H01L29/78603 ,  H01L29/0607

    Abstract: A semiconductor device includes a substrate having a recess therein that is partially filled with at least two semiconductor active regions. The recess has sidewalls and a bottom that are sufficiently lined with corresponding substrate insulating layers that the at least two semiconductor active regions are electrically isolated from the substrate, which surrounds the sidewalls and bottom of the recess. A sidewall insulating layer is provided, which extends as a partition between first and second ones of the at least two semiconductor active regions, such that the first and second ones of the at least two semiconductor active regions are electrically isolated from each other. First and second gate electrodes are provided in the first and second active regions, respectively.

    SEMICONDUCTOR DEVICES WITH ENHANCED SUBSTRATE ISOLATION
    7.
    发明申请
    SEMICONDUCTOR DEVICES WITH ENHANCED SUBSTRATE ISOLATION 有权

    公开(公告)号：US20220376116A1

    公开(公告)日：2022-11-24

    申请号：US17715887

    申请日：2022-04-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sohyeon Lee ,  Sungsu Moon ,  Jaeduk Lee ,  Ikhyung Joo

    IPC: H01L29/786 ,  H01L29/06

    Abstract: A semiconductor device includes a substrate having a recess therein that is partially filled with at least two semiconductor active regions. The recess has sidewalls and a bottom that are sufficiently lined with corresponding substrate insulating layers that the at least two semiconductor active regions are electrically isolated from the substrate, which surrounds the sidewalls and bottom of the recess. A sidewall insulating layer is provided, which extends as a partition between first and second ones of the at least two semiconductor active regions, such that the first and second ones of the at least two semiconductor active regions are electrically isolated from each other. First and second gate electrodes are provided in the first and second active regions, respectively.

    SEMICONDUCTOR DEVICES
    8.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220336501A1

    公开(公告)日：2022-10-20

    申请号：US17854128

    申请日：2022-06-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sohyeon Lee ,  Sungsu Moon ,  Jaeduk Lee ,  Ikhyung Joo

    IPC: H01L27/12 ,  H01L21/84 ,  H01L29/08 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

    Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation film and providing a first channel region; a first source/drain region in the active region on first and second sides of the first channel region; a gate structure having a first gate insulating film, a shared gate electrode, and a second gate insulating film, sequentially arranged on the active region; a cover semiconductor layer on the second gate insulating film and electrically separated from the active region to provide a second channel region; a second source/drain region in the cover semiconductor layer on first and second sides of the second channel region; first and second source/drain contacts respectively connected to the first and second source/drain regions; and a shared gate contact connected to the shared gate electrode.

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