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公开(公告)号:US20240373632A1
公开(公告)日:2024-11-07
申请号:US18406913
申请日:2024-01-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kang Lib Kim , Sungsu Moon , Sea Hoon Lee , Junhee Lim
IPC: H10B43/27 , H01L23/522 , H10B43/40
Abstract: Disclosed are 3D semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a first substrate including a cell array region and a contact region, a stack structure including interlayers and gate electrodes and including a pad part having a stepwise structure on the contact region, a first dielectric layer covering the pad part of the stack structure, a second dielectric layer on the first dielectric layer, an interlayer capacitor between the first dielectric layer and the second dielectric layer, cell contact plugs penetrating the pad part of the stack structure, the first dielectric layer, and the second dielectric layer and correspondingly connected to the gate electrodes, and lower and upper conductive lines penetrating the pad part of the stack structure, the first dielectric layer, and the second dielectric layer and electrically connected to the interlayer capacitor.
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公开(公告)号:US20250048627A1
公开(公告)日:2025-02-06
申请号:US18427977
申请日:2024-01-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jaehyeok Heo , Kyoung-Ho Kim , Hojun Lee , Sungsu Moon , Sea Hoon Lee , Jaeduk Lee , Junhee Lim
Abstract: Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device includes a substrate that has a recess region, a gate electrode on a bottom surface of the recess region, a gate dielectric layer between the gate electrode and the bottom surface of the recess region, a plurality of shield electrodes on laterally opposite sides of the gate electrode and on inner sidewalls of the recess region, a plurality of dielectric patterns between the shield electrodes and the inner sidewalls of the recess region, a plurality of impurity regions in the substrate and on opposite sides of the shield electrodes, and a channel region in the substrate and below the bottom surface of the recess region.
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