公开(公告)号：US20250024677A1

公开(公告)日：2025-01-16

申请号：US18660638

申请日：2024-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang Lib Kim ,  Sungsu Moon ,  Seahoon Lee ,  Junhee Lim

IPC: H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a gate electrode structure, a memory channel structure, and first and second contact plugs. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction, and each of the gate electrodes extends in a second direction. The gate electrode structure has a staircase shape including step layers each of which includes two gate electrodes. The memory channel structure extends through the gate electrode structure. The first contact plug contacts an upper surface of a first gate electrode of the two gate electrodes at an upper level in a corresponding step layer. The second contact plug contacts a sidewall of a second gate electrode of the two gate electrodes at a lower level in the corresponding step layer. The second contact plug extends in the first direction and is electrically insulated from gate electrodes disposed below the second gate electrode.

公开(公告)号：US20240373632A1

公开(公告)日：2024-11-07

申请号：US18406913

申请日：2024-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang Lib Kim ,  Sungsu Moon ,  Sea Hoon Lee ,  Junhee Lim

IPC: H10B43/27 ,  H01L23/522 ,  H10B43/40

Abstract: Disclosed are 3D semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a first substrate including a cell array region and a contact region, a stack structure including interlayers and gate electrodes and including a pad part having a stepwise structure on the contact region, a first dielectric layer covering the pad part of the stack structure, a second dielectric layer on the first dielectric layer, an interlayer capacitor between the first dielectric layer and the second dielectric layer, cell contact plugs penetrating the pad part of the stack structure, the first dielectric layer, and the second dielectric layer and correspondingly connected to the gate electrodes, and lower and upper conductive lines penetrating the pad part of the stack structure, the first dielectric layer, and the second dielectric layer and electrically connected to the interlayer capacitor.