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1.发明授权公开(公告)号：US10862526B2
公开(公告)日：2020-12-08
申请号：US16592525
申请日：2019-10-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jun-Ho Huh , Ho-Rang Jang , Seok-Chan Kim , In-Tae Kang , Sang-Heon Lee , Kwan-Yeob Chae , June-Hee Lee , Sang-Hune Park , Jae-Chol Lee , Hyung-Kweon Lee
Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
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公开(公告)号：US10410874B2
公开(公告)日：2019-09-10
申请号：US15867082
申请日：2018-01-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Beom Jin Yoo , Sang Ki Nam , Kwang-Youb Heo , Jehun Woo , Sang-Heon Lee , Masahiko Tomita , Vasily Pashkovskiy
IPC: H01L21/3065 , H01J37/32 , H01L21/027 , H01L21/67 , H01L21/683 , H01L21/311
Abstract: In a plasma processing method, a substrate is loaded onto a substrate electrode within a chamber, the substrate having an object layer to be etched thereon. A plasma generating power output is applied to form plasma within the chamber. A first bias power output is applied to the substrate electrode to perform a first etch stage on the object layer. A second bias power output having a nonsinusoidal voltage waveform is applied to the substrate electrode to perform a second etch stage on the object layer.
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3.发明授权公开(公告)号：US10050661B2
公开(公告)日：2018-08-14
申请号：US15614667
申请日：2017-06-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jun-Ho Huh , Ho-Rang Jang , Seok-Chan Kim , In-Tae Kang , Sang-Heon Lee , Kwan-Yeob Chae , June-Hee Lee , Sang-Hune Park , Jae-Chol Lee , Hyung-Kweon Lee
Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
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公开(公告)号：US09105581B2
公开(公告)日：2015-08-11
申请号：US14297024
申请日：2014-06-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sam Hyung-sam Kim , Gon-Jun Kim , Volynets Vladmir , Yong-Kyun Park , In-Cheol Song , Sang-Heon Lee , Sang-Jean Jeon
IPC: H01L21/3065 , H01L21/67 , H01L21/3213
CPC classification number: H01L21/67069 , H01J37/32357 , H01J37/3244 , H01L21/32136 , H01L21/6719
Abstract: In a method of processing a substrate, a first plasma may be generated from a first reaction gas. A second plasma may be generated from a second reaction gas. The first plasma and the second plasma may be individually applied to the substrate. Thus, each of the at least two remote plasma sources may generate at least two plasmas under different process recipes, which may be optimized for processing the substrate. As a result, the substrate processed using the optimal plasmas may have a desired shape.
Abstract translation: 在处理衬底的方法中，可以从第一反应气体产生第一等离子体。 可以从第二反应气体产生第二等离子体。 第一等离子体和第二等离子体可以单独地施加到基底。 因此，至少两个远程等离子体源中的每一个可以在不同的工艺配方下产生至少两个等离子体，其可以被优化用于处理衬底。 结果，使用最佳等离子体处理的衬底可以具有期望的形状。
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公开(公告)号：US10916202B2
公开(公告)日：2021-02-09
申请号：US16420688
申请日：2019-05-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyung-Hoon Lee , Sang-Pil Nam , Sang-Heon Lee , Michael Choi
IPC: G09G3/3275 , G09G3/3266 , G01R19/00 , G09G3/3233 , H03F3/45 , H03F1/34 , H03F3/04
Abstract: A high voltage sensing circuit included in a display driver integrated circuit includes a plurality of channels, a plurality of sampling capacitors, an amplifier and a feedback capacitor. The plurality of channels receives a plurality of input voltages. The plurality of sampling capacitors are connected to the plurality of channels, respectively, to simultaneously sample the plurality of input voltages. The amplifier is configured to sequentially receive each of a plurality of sampled input voltages to sequentially generate a respective plurality of sensing voltages. The feedback capacitor is connected between an input terminal and an output terminal of the amplifier, and is shared by the plurality of channels. The amplifier and the feedback capacitor are configured such that each of the plurality of sampled input voltages is sequentially scaled to the respective one of the plurality of sensing voltages by the amplifier and the feedback capacitor.
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Patent Agency Ranking
公开(公告)号：US10547322B2
公开(公告)日：2020-01-28
申请号：US16186761
申请日：2018-11-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Heon Lee , Michael Choi
Abstract: An analog-digital converter has multiple feedback, and includes: a capacitor digital-analog converter including a plurality of switches driven by a digital code, and a plurality of capacitors respectively connected to the plurality of switches, wherein the capacitor digital-analog converter is configured to generate a residue voltage based on an analog input voltage and a voltage corresponding to the digital code; first and second feedback capacitors each storing the residue voltage; an integrator configured to generate an integral signal by integrating the residue voltage; first and second comparators respectively configured to generate first and second comparison signals from the integral signal; and a digital logic circuitry configured to receive the first and second comparison signals, and generate a digital output signal from the first and second comparison signals, the digital output signal corresponding to the digital code during a successive approximation register (SAR) analog-digital conversion interval, and the digital output signal corresponding to an average of first and second digital control signals during a delta sigma analog-digital conversion interval, wherein the first and second comparison signals are respectively fed back to the first and second feedback capacitors. The analog-digital converter may be included in various electronic devices, including communication devices.
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7.发明授权公开(公告)号：US10516433B2
公开(公告)日：2019-12-24
申请号：US16037024
申请日：2018-07-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jun-Ho Huh , Ho-Rang Jang , Seok-Chan Kim , In-Tae Kang , Sang-Heon Lee , Kwan-Yeob Chae , June-Hee Lee , Sang-Hune Park , Jae-Chol Lee , Hyung-Kweon Lee
Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
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8.发明申请公开(公告)号：US20190035606A1
公开(公告)日：2019-01-31
申请号：US15867082
申请日：2018-01-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Beom Jin Yoo , Sang Ki Nam , Kwang-Youb Heo , Jehun Woo , Sang-Heon Lee , Masahiko Tomita , Vasily Pashkovskiy
IPC: H01J37/32 , H01L21/027 , H01L21/67 , H01L21/683 , H01L21/311
CPC classification number: H01L21/3065 , H01J37/32128 , H01J37/32146 , H01J37/32165 , H01J37/32174 , H01J37/32724 , H01J2237/334 , H01L21/0273 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/67069 , H01L21/67103 , H01L21/67109 , H01L21/67248 , H01L21/6831 , H01L21/6833
Abstract: In a plasma processing method, a substrate is loaded onto a substrate electrode within a chamber, the substrate having an object layer to be etched thereon. A plasma generating power output is applied to form plasma within the chamber. A first bias power output is applied to the substrate electrode to perform a first etch stage on the object layer. A second bias power output having a nonsinusoidal voltage waveform is applied to the substrate electrode to perform a second etch stage on the object layer.
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公开(公告)号：US20180144506A1
公开(公告)日：2018-05-24
申请号：US15622927
申请日：2017-06-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Heon Lee , Yeon-Gon Cho , Soo-Jung Ryu
Abstract: A texture processing method and apparatus that obtains information about a first data loss amount that occurred during a texture compression process. A determination is made regarding a second data loss amount that allowable during a texture filtering process based on the obtained information regarding the first data loss amount. Texture filtering is then performed by using the second data loss amount. At least one processor determines the second data loss amount based on a difference between the third data loss amount and the first data loss amount.
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公开(公告)号：US09256949B2
公开(公告)日：2016-02-09
申请号：US13919384
申请日：2013-06-17
Inventor： Sang-Heon Lee , Soo-Jung Ryu , Yeon-Gon Cho , Do-Hyun Kim , Yeong-Gil Shin , Byeong-Hun Lee
IPC: G06T7/00
CPC classification number: G06T7/0081 , G06T7/11 , G06T2207/10081
Abstract: A region growing apparatus using multi-core includes a plurality of cores, each core including an operation controller configured to perform an operation for region growing of a 2D pixel region or 3D pixel region and an inner memory configured to store a queue associated with a seed pixel as a target of the operation; and a shared memory connected to the plurality of cores over a network and shared by the plurality of cores.
Abstract translation: 使用多核的区域生长装置包括多个核心，每个核心包括被配置为执行2D像素区域或3D像素区域的区域生长的操作的操作控制器和被配置为存储与种子相关联的队列的内部存储器 像素作为操作的目标; 以及通过网络连接到所述多个核并由所述多个核共享的共享存储器。
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