公开(公告)号：US20250015065A1

公开(公告)日：2025-01-09

申请号：US18425332

申请日：2024-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam KANG

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a wiring structure including at least one first wiring layer and at least one first insulating layer, a semiconductor chip overlapping the wiring structure in a vertical direction, a second insulating layer overlapping the wiring structure in the vertical direction and including a cavity, an inductor in the cavity and electrically connected to the semiconductor chip, a lead-out pillar extending from one surface of the inductor facing the wiring structure and electrically connecting the inductor and the semiconductor chip, and an encapsulant encapsulating the inductor, wherein the inductor includes an insulating body and a coil portion in the insulating body, and configured to output a magnetic field in a direction, different from the vertical direction, and a region on one surface of the insulating body not overlapping the lead-out pillar is in direct contact with the encapsulant or the at least one first insulating layer.

公开(公告)号：US20230154836A1

公开(公告)日：2023-05-18

申请号：US18098158

申请日：2023-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Youngchan KO ,  Jeongseok KIM ,  Kyung Don MUN ,  Bongju CHO

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/3171 ,  H01L24/16 ,  H01L23/5386 ,  H01L2224/16235

Abstract: A semiconductor package includes a redistribution substrate having a dielectric layer and a wiring pattern in the dielectric layer, the wiring pattern including a line part that extends horizontally, and a via part connected to the line part, the via part having a width less than a width of the line part, a passivation layer on a top surface of the redistribution substrate, the passivation layer including a material different from a material of the dielectric layer, a conductive pillar that penetrates the passivation layer, the conductive pillar being connected to the via part, and a connection terminal on a top surface of the conductive pillar, a distance between the top surface of the conductive pillar and a top surface of the passivation layer being greater than a thickness of the passivation layer.

公开(公告)号：US20250087637A1

公开(公告)日：2025-03-13

申请号：US18617896

申请日：2024-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsam KANG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L23/15 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H01L25/16

Abstract: A semiconductor package includes a redistribution substrate, a glass substrate mounted on the redistribution substrate and including a cavity in a central portion of the glass substrate, a bridge die in the cavity, a first semiconductor chip and a second semiconductor chip, the first semiconductor chip and the second semiconductor chip side by side, on the glass substrate, and the first semiconductor chip and the second semiconductor chip on the bridge die, a mold layer covering a top surface of the redistribution substrate, the glass substrate, the bridge die, the first semiconductor chip and the second semiconductor chip, and internal connection terminals connecting the glass substrate and the bridge die to the first and second semiconductor chips. The glass substrate includes a plurality of connection vias. A distance between an outer side surface of the glass substrate and a side surface of the mold layer ranges from 30 μm to 500 μm.

公开(公告)号：US20220262748A1

公开(公告)日：2022-08-18

申请号：US17737472

申请日：2022-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Changbae Lee ,  Bongju Cho ,  Younggwan Ko ,  Yongkoon Lee ,  Moonil Kim ,  Youngchan Ko

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/522

Abstract: A semiconductor package includes: a connection structure having a first surface and a second, and including a redistribution layer; a passive component disposed on the first surface of the connection structure, and electrically connected to the redistribution layer; a semiconductor chip disposed on the first surface of the connection structure, and electrically connected to the redistribution layer; a first encapsulant disposed on the first surface of the connection structure and covering at least a portion of the semiconductor chip; a second encapsulant disposed on the first surface of the connection structure and covering at least a portion of the passive component; an antenna substrate disposed on the first encapsulant and including a wiring layer, at least a portion of the wiring layer including an antenna pattern; and a through via penetrating at least a portion of each of the connection structure, the first encapsulant, and the antenna substrate.

公开(公告)号：US20220246506A1

公开(公告)日：2022-08-04

申请号：US17685227

申请日：2022-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjin PARK ,  Myungsam KANG ,  Younggwan KO

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

Abstract: A package module includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and having a connection pad electrically connected to the one or more redistribution layers, a plurality of electronic components disposed on the connection structure and electrically connected to the one or more redistribution layers, one or more frames disposed on the connection structure, and an encapsulant disposed on the connection structure, and respectively covering at least portions of the semiconductor chip, the plurality of electronic components, and the one or more frames. At least a portion of an outer side surface of the encapsulant is coplanar on the same level as at least a portion of an outer side surface of at least one of the one or more frames.

公开(公告)号：US20210398923A1

公开(公告)日：2021-12-23

申请号：US17154041

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Sangkyu LEE ,  Yongkoon LEE

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/22 ,  H01Q1/52

Abstract: A semiconductor package includes a front redistribution structure having a first surface and a second surface, opposite to the first surface, a dielectric layer, an antenna substrate including a plurality of antenna members in the dielectric layer, a semiconductor chip having a connection pad connected to the plurality of antenna members, a conductive core structure having a first through-hole accommodating the antenna substrate and a second through-hole accommodating the semiconductor chip, and a rear redistribution structure including a conductive cover layer exposing an upper portion of the antenna substrate and covering an upper portion of the semiconductor chip, and a conductive via connecting the conductive cover layer to the conductive core structure.

公开(公告)号：US20250046755A1

公开(公告)日：2025-02-06

申请号：US18740075

申请日：2024-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Chilwoo KWON ,  Okgyeong PARK

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H10B80/00

Abstract: A semiconductor package includes a ceramic substrate having a cavity, a lower redistribution structure on a lower surface of the ceramic substrate and electrically connected to the ceramic substrate, an upper redistribution structure on an upper surface of the ceramic substrate and electrically connected to the ceramic substrate, a plurality of semiconductor chips arranged in a first direction on the upper redistribution structure, and a bridge chip structure in the cavity of the ceramic substrate and including a bridge chip electrically connecting the plurality of semiconductor chips to each other.

公开(公告)号：US20240030118A1

公开(公告)日：2024-01-25

申请号：US18224948

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG

IPC: H01L23/498 ,  H01L23/15 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/49822 ,  H01L23/15 ,  H01L28/60 ,  H01L23/49811 ,  H01L25/0652 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L24/16

Abstract: A package substrate includes a ceramic substrate including a plurality of first insulating layers and a first circuit wiring layer disposed in the plurality of first insulating layers, a redistribution structure disposed on an upper surface of the ceramic substrate, and including a plurality of second insulating layers and a second circuit wiring layer disposed in the plurality of second insulating layers and electrically connected to the first circuit wiring layer, and a capacitor structure provided at an interface between the ceramic substrate and the redistribution structure, and including a lower electrode layer disposed at the same vertical level as at least a portion of the first circuit wiring layer, a dielectric layer disposed between the ceramic substrate and the redistribution structure, and an upper electrode layer disposed on an upper surface of the dielectric layer.

公开(公告)号：US20230411275A1

公开(公告)日：2023-12-21

申请号：US18096132

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49894 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H05K2203/1316 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/182 ,  H01L24/16

Abstract: A semiconductor package includes stacked wiring layers, a lower substrate pad on a bottom surface of a lowermost wiring layer, a protection layer covering the lower substrate pad on the bottom surface of the lowermost wiring layer, a dielectric layer on a top surface of an uppermost wiring layer, an upper substrate pad on the dielectric layer, a semiconductor chip on the upper substrate pad, and a molding layer covering the semiconductor chip on the uppermost wiring layer. Each of the wiring layers includes a dielectric pattern and a wiring pattern therein. The protection layer has openings that expose the lower substrate pad. A thickness of the dielectric layer is less than that of the dielectric pattern in the wiring layers. A thickness of the upper substrate pad is less than that of the wiring pattern in the wiring layers.

公开(公告)号：US20230187399A1

公开(公告)日：2023-06-15

申请号：US18166869

申请日：2023-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungsam KANG ,  Youngchan KO ,  Jeongseok KIM ,  Kyungdon MUN

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L24/05 ,  H01L23/49811 ,  H01L23/5226

Abstract: A semiconductor package includes a redistribution structure including an insulating layer and a redistribution layer on the insulating layer, and having a first surface and a second surface opposing the first surface, and an under-bump metal (UBM) structure including an UBM pad protruding from the first surface of the redistribution structure, and an UBM via penetrating through the insulating layer and connecting the redistribution layer and the UBM pad. A lower surface of the UBM via has a first area in contact with the UBM pad, and a second area having a step configuration relative to the first area and that extends outwardly of the first area.