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    METHOD AND TERMINAL FOR PROVIDING A ROUTE IN A NAVIGATION SYSTEM USING SATELLITE IMAGE
    3.
    发明申请
    METHOD AND TERMINAL FOR PROVIDING A ROUTE IN A NAVIGATION SYSTEM USING SATELLITE IMAGE 有权
    使用卫星图像在导航系统中提供路由的方法和终端

    公开(公告)号：US20130297209A1

    公开(公告)日：2013-11-07

    申请号：US13930389

    申请日：2013-06-28

    Applicant: SAMSUNG ELECTRONICS CO. LTD.

    Inventor： Hyun-Suk MIN ,  Hee JUNG ,  Kwang-Soo KIM ,  Jin-Won KIM

    IPC: G01C21/00

    CPC classification number: G01C21/00 ,  G01C21/3647

    Abstract: A method and a terminal for providing a route in a navigation system using a satellite image are provided. The terminal includes a route calculation unit for calculating a route from a current location to a destination when a user inputs the destination, a satellite image requesting unit for requesting a satellite image server for satellite images corresponding to locations on the route and for downloading the requested satellite images, a satellite image storage unit for storing the downloaded satellite images, and a controller for retrieving a satellite image corresponding to the current location from the satellite image storage unit and for displaying the retrieved satellite image simultaneously while downloading the satellite images corresponding to the locations on the route.

    Abstract translation: 提供了一种使用卫星图像在导航系统中提供路线的方法和终端。 终端包括路由计算单元，用于当用户输入目的地时计算从当前位置到目的地的路线;卫星图像请求单元，用于请求卫星图像服务器，用于与路线上的位置相对应的卫星图像，并且下载所请求的 卫星图像，用于存储下载的卫星图像的卫星图像存储单元，以及用于从卫星图像存储单元检索与当前位置相对应的卫星图像并用于同时显示所检索的卫星图像的控制器，同时下载对应于卫星图像的卫星图像 路线上的位置。

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200075605A1

    公开(公告)日：2020-03-05

    申请号：US16403795

    申请日：2019-05-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junhyoung KIM ,  Kwang-Soo KIM ,  Bonghyun CHOI ,  Siwan KIM

    IPC: H01L27/115

    Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

    MEMORY CARDS AND STORAGE SYSTEMS INCLUDING THE SAME
    6.
    发明申请
    MEMORY CARDS AND STORAGE SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20180088865A1

    公开(公告)日：2018-03-29

    申请号：US15652811

    申请日：2017-07-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： In-Jae LEE ,  Kwang-Soo KIM ,  Hyong-Woo YU

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/16 ,  G06K19/0712 ,  G06K19/07732 ,  G06K19/07743 ,  G11C7/1042 ,  G11C7/22 ,  G11C16/30 ,  G11C2207/2209

    Abstract: A memory card includes first and second groups of terminals, at least one controller, and first and second nonvolatile memories. The first group of terminals are adjacent to an edge at an insertion side of a substrate and include a first power terminal to provide a first voltage. The second group of terminals is spaced farther apart from the edge at the insertion side than the first group of terminals and includes a second power terminal to provide a second voltage. The at least one memory controller is connected to the first and second groups of terminals, and the first and second nonvolatile memories are independently connected to the at least one controller. The at least one controller simultaneously accesses the first nonvolatile memory and the second nonvolatile memory when the first group of terminals and the second group of terminals are connected to an external host.

    SEMICONDUCTOR PACKAGE INCLUDING BACKSIDE POWER DELIVERY NETWORK LAYER
    7.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING BACKSIDE POWER DELIVERY NETWORK LAYER 有权

    公开(公告)号：US20250087646A1

    公开(公告)日：2025-03-13

    申请号：US18606888

    申请日：2024-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsoo CHUNG ,  Kwang-Soo KIM ,  Jaesic LEE

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538

    Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, a first mold layer at least partially covering the first redistribution substrate and the first semiconductor chip, a plurality of first conductive pillars at least partially penetrating the first mold layer and contacting the first redistribution substrate, a second redistribution substrate on the first mold layer, a second semiconductor chip on the second redistribution substrate, a second mold layer at least partially covering the second redistribution substrate and the second semiconductor chip, a plurality of second conductive pillars at least partially penetrating the second mold layer and contacting the second redistribution substrate, and a third redistribution substrate on the second mold layer. The first semiconductor chip includes a first through via. The second semiconductor chip includes a backside power delivery network layer.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    8.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190393241A1

    公开(公告)日：2019-12-26

    申请号：US16272288

    申请日：2019-02-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seokcheon BAEK ,  Kwang-Soo KIM

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L21/768 ,  H01L29/423 ,  H01L23/522 ,  H01L23/528

    Abstract: Three-dimensional semiconductor memory devices are provided. The devices may include a semiconductor layer and electrode structures on the semiconductor layer. The electrode structures may include a first electrode structure including a first electrode portion and a first pad portion and a second electrode structure including a second electrode portion and a second pad portion. Each of the first and second electrode portions has a first width, each of the first and second pad portions has a second width, and the second width may be less than the first width. The first and second electrode portions may be spaced apart from each other by a first distance, and the first and second pad portions may be spaced apart from each other by a second distance that may be greater than the first distance.

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