公开(公告)号：US20160351517A1

公开(公告)日：2016-12-01

申请号：US15164502

申请日：2016-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongbin SHI ,  Kang Joon LEE

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02135 ,  H01L2224/02145 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/06131 ,  H01L2224/0615 ,  H01L2224/1131 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/14131 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An electric apparatus may include a plurality of electric patterns arranged on a substrate. Each of the electric patterns may include a pad for connection with a solder ball, an electrical trace laterally extending from a portion of the pad to allow an electrical signal to be transmitted from or to the pad, a first dummy trace laterally extending from other portion of the pad, and a first connection line connecting the first dummy trace to the electrical trace. The first dummy trace may be provided at a position deviated from a straight line connecting the pad to the electrical trace.

Abstract translation: 电气设备可以包括布置在基板上的多个电图案。 每个电图案可以包括用于与焊球连接的焊盘，从焊盘的一部分横向延伸的电迹线以允许电信号从焊盘或从焊盘传输，第一虚拟焊盘从其他部分横向延伸 以及将第一虚拟轨迹连接到电迹线的第一连接线。 可以将第一虚拟轨迹设置在偏离连接焊盘与电迹线的直线的位置处。

公开(公告)号：US20250062264A1

公开(公告)日：2025-02-20

申请号：US18623202

申请日：2024-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihyun LEE ,  Kang Joon LEE ,  Seokwon LEE

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/60

Abstract: A semiconductor package including a first structure, a second structure, and an interconnect structure between the first structure and the second structure. The interconnect structure includes a first region extending from a center of the interconnect structure to a first distance, and a second region outside the first region. The interconnect structure includes a plurality of first connection members in the first region and a plurality of second connection members in the second region. The plurality of first connection members are arranged in a staggered form, and the plurality of second connection members are arranged in rows.

公开(公告)号：US20160240509A1

公开(公告)日：2016-08-18

申请号：US15135364

申请日：2016-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heungkyu KWON ,  Kang Joon LEE ,  JaeWook YOO ,  Su-Chang LEE

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/13 ,  H01L23/16 ,  H01L23/18 ,  H01L23/3157 ,  H01L23/488 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13541 ,  H01L2224/13561 ,  H01L2224/13583 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13649 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/1712 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/1751 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2224/05552

Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.

Abstract translation: 半导体封装包括包括中心部分和周边部分的第一基板，附接到第一基板的中心部分的至少一个第一中心连接部件和附接到第一基板的周边部分的至少一个第一周边连接部件。 第一中心连接构件包括第一支撑件和围绕第一支撑件的第一融合导电层。

公开(公告)号：US20240145295A1

公开(公告)日：2024-05-02

申请号：US18226372

申请日：2023-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihyun LEE ,  Junho LEE ,  Kang Joon LEE

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L25/18

CPC classification number: H01L21/768 ,  H01L21/565 ,  H01L23/49816 ,  H01L23/53209 ,  H01L24/48 ,  H01L25/18 ,  H01L2224/48151 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: A semiconductor package includes a first structure that includes an upper connection pattern; a second structure that includes a lower connection pattern; and a connection structure that connects the upper connection pattern of the first structure to the lower connection pattern of the second structure, wherein the connection structure includes a lower conductor connected to the upper connection pattern of the first structure; an upper conductor connected to the lower conductor and the lower connection pattern of the second structure; and a dielectric pattern that at least partially surrounds the upper conductor, and the dielectric pattern includes a first surface in contact with the upper conductor; and a second surface in contact with the lower conductor.