公开(公告)号：US20230274776A1

公开(公告)日：2023-08-31

申请号：US18314243

申请日：2023-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G11C11/409 ,  G06F3/0673 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0604 ,  G11C7/222

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20220383931A1

公开(公告)日：2022-12-01

申请号：US17816138

申请日：2022-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C7/22 ,  G11C11/409 ,  G06F3/06

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20200135247A1

公开(公告)日：2020-04-30

申请号：US16721131

申请日：2019-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  SI-HONG KIM ,  CHANG-KYO LEE ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA

IPC: G11C7/24 ,  G11C7/10 ,  H03H7/38

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

公开(公告)号：US20250157504A1

公开(公告)日：2025-05-15

申请号：US18977329

申请日：2024-12-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHUN LEE ,  DAESIK MOON ,  YOUNG-SOO SOHN ,  YOUNG-HOON SON ,  KI-SEOK OH ,  CHANGKYO LEE ,  HYUN-YOON CHO ,  KYUNG-SOO HA ,  SEOKHUN HYUN

IPC: G11C7/10 ,  G06F3/06 ,  G11C29/02 ,  G11C29/50

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

公开(公告)号：US20190027206A1

公开(公告)日：2019-01-24

申请号：US16039400

申请日：2018-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HWA KIM ,  TAE-YOUNG OH ,  JIN-HUN JANG ,  SEOK-JIN CHO ,  KYUNG-SOO HA

IPC: G11C11/4074 ,  G11C5/14

CPC classification number: G11C11/4074 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G11C5/147

Abstract: A memory device has a plurality of power rails, including: a first power rail for transmitting a high power voltage, a second power rail for transmitting a low power voltage, a third power rail for selectively receiving the high power voltage from the first power rail through a first dynamic voltage and frequency scaling (DVFS) switch and for selectively receiving the low power voltage from the second power rail through a second DVFS switch, a fourth power rail connected to a first power gating (PG) switch to selectively receive the high power voltage or the low power voltage from the third power rail, and a first circuit block connected to the fourth power rail to receive a power voltage to which the DVFS and PG are applied. When power gating is applied, supply of the power voltage to the fourth power rail is blocked.

公开(公告)号：US20220122648A1

公开(公告)日：2022-04-21

申请号：US17564564

申请日：2021-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20210166749A1

公开(公告)日：2021-06-03

申请号：US17148915

申请日：2021-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20210082479A1

公开(公告)日：2021-03-18

申请号：US17104114

申请日：2020-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  KYUNG-SOO HA ,  YOUNG-SOO SOHN ,  KI-SEOK OH ,  CHANG-KYO LEE ,  JIN-HOON JANG ,  YEON-KYU CHOI ,  SEOK-HUN HYUN

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US20200243123A1

公开(公告)日：2020-07-30

申请号：US16848364

申请日：2020-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  SI-HONG KIM ,  CHANG-KYO LEE ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA

IPC: G11C7/24 ,  H03H7/38 ,  G11C7/10

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on;enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

公开(公告)号：US20240420754A1

公开(公告)日：2024-12-19

申请号：US18817678

申请日：2024-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G06F3/06 ,  G11C7/22 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.